diff --git a/alu_tb.vhdl b/alu_tb.vhdl
index b1c3bc6..8140258 100644
--- a/alu_tb.vhdl
+++ b/alu_tb.vhdl
@@ -3,10 +3,10 @@ use ieee.math_real.all;
 use ieee.numeric_std.all;
 use ieee.std_logic_1164.all;
 
-entity ALU is
-end ALU;
+entity ALU_tb is
+end ALU_tb;
 
-architecture Structurel of ALU is
+architecture Structurel of ALU_tb is
 
   --! ########   signals for component    ########
  
@@ -33,7 +33,7 @@ architecture Structurel of ALU is
   end function;
 
 begin
-  alu_0 : entity work.alu
+  alu_0 : entity work.ALU
     port map(
       op1  => op1,
       op2  => op2,