diff --git a/e~shifter_tb.o b/e~shifter_tb.o new file mode 100644 index 0000000..3a76726 Binary files /dev/null and b/e~shifter_tb.o differ diff --git a/shifter.o b/shifter.o new file mode 100644 index 0000000..55d7289 Binary files /dev/null and b/shifter.o differ diff --git a/shifter.vcd b/shifter.vcd new file mode 100644 index 0000000..59cdce2 --- /dev/null +++ b/shifter.vcd @@ -0,0 +1,62 @@ +$date + Wed Oct 27 12:29:22 2021 +$end +$version + GHDL v0 +$end +$timescale + 1 fs +$end +$var reg 1 ! shift_lsl $end +$var reg 1 " shift_lsr $end +$var reg 1 # shift_asr $end +$var reg 1 $ shift_ror $end +$var reg 1 % shift_rrx $end +$var reg 5 & shift_val[4:0] $end +$var reg 32 ' din[31:0] $end +$var reg 1 ( cin $end +$var reg 32 ) dout[31:0] $end +$var reg 1 * cout $end +$var reg 1 + vdd $end +$var reg 1 , vss $end +$scope module shift $end +$var reg 1 - shift_lsl $end +$var reg 1 . shift_lsr $end +$var reg 1 / shift_asr $end +$var reg 1 0 shift_ror $end +$var reg 1 1 shift_rrx $end +$var reg 5 2 shift_val[4:0] $end +$var reg 32 3 din[31:0] $end +$var reg 1 4 cin $end +$var reg 32 5 dout[31:0] $end +$var reg 1 6 cout $end +$var reg 1 7 vdd $end +$var reg 1 8 vss $end +$upscope $end +$enddefinitions $end +#0 +0! +0" +0# +1$ +0% +b00010 & +b00000000000000000111111110001110 ' +0( +b10000000000000000001111111100011 ) +1* +1+ +0, +0- +0. +0/ +10 +01 +b00010 2 +b00000000000000000111111110001110 3 +04 +b10000000000000000001111111100011 5 +16 +17 +08 +#5000000 diff --git a/shifter.vhdl b/shifter.vhdl index e69de29..c31e11e 100644 --- a/shifter.vhdl +++ b/shifter.vhdl @@ -0,0 +1,283 @@ +library ieee; +use ieee.math_real.all; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +entity Shifter is + port( + shift_lsl : in Std_Logic; + shift_lsr : in Std_Logic; + + shift_asr : in Std_Logic; + + shift_ror : in Std_Logic; -- rotation sans extension + shift_rrx : in Std_Logic; -- avec extension + + shift_val : in Std_Logic_Vector(4 downto 0); + + din : in Std_Logic_Vector(31 downto 0); + cin : in Std_Logic; + + dout : out Std_Logic_Vector(31 downto 0); + cout : out Std_Logic; + + -- global interface + vdd : in bit; + vss : in bit ); +end Shifter; + +-- TODO: +-- changer les "000" et "temp_dout(31)& temp_dout(31)& ..." par la synthaxe +-- (n1 downto n0 => '0') ou (n1 downto n0 => '0') + +architecture Shifter_bhvr of Shifter is + begin + process(shift_lsl, shift_lsr, shift_asr, shift_ror, shift_rrx,shift_val, + din, cin, vdd, vss) + variable temp_dout : Std_Logic_Vector(31 downto 0); + variable temp_cout : Std_Logic; + begin + temp_dout := din; + temp_cout := cin; + -- LSL ------------------------------------------------------------- + -- 1 + if(shift_lsl='1' and shift_val(0)='1') + then + temp_cout := temp_dout(31); + temp_dout := (temp_dout(30 downto 0)&'0'); + else NULL; + end if; + + -- 2 + if(shift_lsl='1' and shift_val(1)='1') + then + temp_cout := temp_dout(30); + temp_dout := (temp_dout(29 downto 0)&"00"); + else NULL; + end if; + + -- 4 + if(shift_lsl='1' and shift_val(2)='1') + then + temp_cout := temp_dout(28); + temp_dout := (temp_dout(27 downto 0)&"0000"); + else NULL; + end if; + + -- 8 + if(shift_lsl='1' and shift_val(3)='1') + then + temp_cout := temp_dout(24); + temp_dout :=(temp_dout(23 downto 0)&"00000000"); + else NULL; + end if; + -- 16 + if(shift_lsl='1' and shift_val(4)='1') + then + temp_cout := temp_dout(16); + temp_dout := + (temp_dout(15 downto 0)&"0000000000000000"); + else NULL; + end if; + + -- LSR ------------------------------------------------------------- + -- 1 + if(shift_lsr='1' and shift_val(0)='1') + then + temp_cout := temp_dout(0); + temp_dout := ('0'&temp_dout(31 downto 1)); + else NULL; + end if; + + -- 2 + if(shift_lsr='1' and shift_val(1)='1') + then + temp_cout := temp_dout(0); + temp_dout := ("00"&temp_dout(31 downto 2)); + else NULL; + end if; + + -- 4 + if(shift_lsr='1' and shift_val(2)='1') + then + temp_cout := temp_dout(0); + temp_dout := ("0000"&temp_dout(31 downto 4)); + else NULL; + end if; + + -- 8 + if(shift_lsr='1' and shift_val(3)='1') + then + temp_cout := temp_dout(0); + temp_dout :=("00000000"&temp_dout(31 downto 8)); + else NULL; + end if; + + -- 16 + if(shift_lsr='1' and shift_val(4)='1') + then + temp_cout := temp_dout(0); + temp_dout := + ("0000000000000000"&temp_dout(31 downto 16)); + else NULL; + end if; + + + -- ASR ------------------------------------------------------------- + -- 1 + if(shift_asr='1' and shift_val(0)='1') + then + temp_cout := temp_dout(0); + temp_dout := (temp_dout(31) + &temp_dout(31 downto 1)); + else NULL; + end if; + + -- 2 + if(shift_asr='1' and shift_val(1)='1') + then + temp_cout := temp_dout(0); + temp_dout := + ( temp_dout(31)& temp_dout(31) + &temp_dout(31 downto 2)); + else NULL; + end if; + + -- 4 + if(shift_asr='1' and shift_val(2)='1') + then + temp_cout := temp_dout(0); + temp_dout := + ( temp_dout(31)& temp_dout(31) + &temp_dout(31)& temp_dout(31) + &temp_dout(27 downto 0)); + else NULL; + end if; + + -- 8 + if(shift_asr='1' and shift_val(3)='1') + then + temp_cout := temp_dout(0); + temp_dout := + ( temp_dout(31)&temp_dout(31)&temp_dout(31) + &temp_dout(31)&temp_dout(31)&temp_dout(31) + &temp_dout(31)&temp_dout(31) + &temp_dout(23 downto 0)); + else NULL; + end if; + + -- 16 + if(shift_asr='1' and shift_val(4)='1') + then + temp_cout := temp_dout(0); + temp_dout := + ( temp_dout(31)& temp_dout(31)& + temp_dout(31)& temp_dout(31)& + temp_dout(31)& temp_dout(31)& + temp_dout(31)& temp_dout(31)& + temp_dout(31)& temp_dout(31)& + temp_dout(31)& temp_dout(31)& + temp_dout(31)& temp_dout(31)& + temp_dout(31)& temp_dout(31)& + temp_dout(15 downto 0)); + else NULL; + end if; + + -- ROR ------------------------------------------------------------- + -- 1 + if(shift_ror='1' and shift_val(0)='1') + then temp_dout := (temp_dout(0) + &temp_dout(31 downto 1)); + temp_cout := temp_dout(0); + else NULL; + end if; + + -- 2 + if(shift_ror='1' and shift_val(1)='1') + then temp_dout := + (temp_dout(1 downto 0) + &temp_dout(31 downto 2)); + temp_cout := temp_dout(1); + else NULL; + end if; + + -- 4 + if(shift_ror='1' and shift_val(2)='1') + then temp_dout := + (temp_dout(3 downto 0) + &temp_dout(31 downto 4)); + temp_cout := temp_dout(3); + else NULL; + end if; + + -- 8 + if(shift_ror='1' and shift_val(3)='1') + then temp_dout := + (temp_dout(7 downto 0) + &temp_dout(31 downto 8)); + temp_cout := temp_dout(7); + else NULL; + end if; + + -- 16 + if(shift_ror='1' and shift_val(4)='1') + then temp_dout := + (temp_dout(15 downto 0) + &temp_dout(31 downto 16)); + temp_cout := temp_dout(15); + else NULL; + end if; + + -- RRX ------------------------------------------------------------- + -- 1 + if(shift_rrx='1' and shift_val(0)='1') + then temp_dout := (temp_cout + &temp_dout(31 downto 1)); + temp_cout := temp_dout(0); + else NULL; + end if; + + -- 2 + if(shift_rrx='1' and shift_val(1)='1') + then temp_dout := + (temp_cout + &temp_dout(0) + &temp_dout(31 downto 2)); + temp_cout := temp_dout(1); + else NULL; + end if; + + -- 4 + if(shift_rrx='1' and shift_val(2)='1') + then temp_dout := + (temp_cout + &temp_dout(2 downto 0) + &temp_dout(31 downto 4)); + temp_cout := temp_dout(3); + else NULL; + end if; + + -- 8 + if(shift_rrx='1' and shift_val(3)='1') + then temp_dout := + (temp_cout + &temp_dout(6 downto 0) + &temp_dout(31 downto 8)); + temp_cout := temp_dout(7); + else NULL; + end if; + + -- 16 + if(shift_rrx='1' and shift_val(4)='1') + then temp_dout := + (temp_cout + &temp_dout(14 downto 0) + &temp_dout(31 downto 16)); + temp_cout := temp_dout(15); + else NULL; + end if; + + cout <= temp_cout; + dout <= temp_dout; + end process; +end Shifter_bhvr; diff --git a/shifter_tb b/shifter_tb new file mode 100755 index 0000000..12f4793 Binary files /dev/null and b/shifter_tb differ diff --git a/shifter_tb.o b/shifter_tb.o new file mode 100644 index 0000000..d7d22c2 Binary files /dev/null and b/shifter_tb.o differ diff --git a/shifter_tb.vhdl b/shifter_tb.vhdl index e69de29..fc43d87 100644 --- a/shifter_tb.vhdl +++ b/shifter_tb.vhdl @@ -0,0 +1,49 @@ +library ieee; +use ieee.math_real.all; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +entity shifter_tb is +end shifter_tb; + +ARCHITECTURE Structurel OF Shifter_tb is +signal shift_lsl : Std_Logic := '0'; +signal shift_lsr : Std_Logic := '0'; +signal shift_asr : Std_Logic := '0'; +signal shift_ror : Std_Logic := '0'; +signal shift_rrx : Std_Logic := '0'; +signal shift_val : Std_Logic_Vector(4 downto 0); +signal din : Std_Logic_Vector(31 downto 0); +signal cin : Std_Logic := '0'; +signal dout : Std_Logic_Vector(31 downto 0); +signal cout : Std_Logic; +signal vdd : bit := '1'; +signal vss : bit := '0'; +begin + +shift: entity work.Shifter +port map( + shift_lsl => shift_lsl, + shift_lsr => shift_lsr, + shift_asr => shift_asr, + shift_ror => shift_ror, + shift_rrx => shift_rrx, + shift_val => shift_val, + din => din, + cin => cin, + dout => dout, + cout => cout, + vdd => vdd, + vss => vss + ); +process +begin + shift_ror <= '1'; + shift_val <= "00010"; + din <= std_logic_vector(to_unsigned(32654, 32)); + wait for 5 ns; + report "dout = " & integer'image(to_integer(unsigned(dout))); + WAIT; +end process; + +end Structurel; diff --git a/work-obj93.cf b/work-obj93.cf new file mode 100644 index 0000000..756601d --- /dev/null +++ b/work-obj93.cf @@ -0,0 +1,7 @@ +v 4 +file . "shifter_tb.vhdl" "91f07b86fce3e94d1a78f6ff81549324e4c127b6" "20211027102922.006": + entity shifter_tb at 1( 0) + 0 on 69; + architecture structurel of shifter_tb at 9( 132) + 0 on 70; +file . "shifter.vhdl" "19ae95a81c4d07ea688fa5629b00a8ab21404624" "20211027101726.934": + entity shifter at 1( 0) + 0 on 53; + architecture shifter_bhvr of shifter at 33( 791) + 0 on 54;