WIP tests

Makefile

@@ -1,29 +1,29 @@
 GHDL = ghdl
-all : sim_adder32 sim_alu sim_shifter
+all : adder32_tb
 
-%.o:	%.vhdl
-	${GHDL} -a -v $<
+# %.o : %.vhdl
+# 	${GHDL} -a -g -v $^
 
-# adder1.o : adder1bit.vhdl
-# 	${GHDL} -a -v adder1bit.vhdl
+adder1.o : adder1.vhdl
+	${GHDL} -a -v adder1.vhdl
 
-# adder32.o : adder_32bit.vhdl adder1bit.o
-# 	${GHDL} -a -v adder_32bit.vhdl
+adder32.o : adder32.vhdl adder1.o
+	${GHDL} -a -v adder32.vhdl
 
-# adder32_tb.o : adder_32bit_tb.vhdl adder_32bit.o
-# 	${GHDL} -a -v adder_32bit_tb.vhdl
+adder32_tb.o : adder32_tb.vhdl adder32.o
+	${GHDL} -a -v adder32_tb.vhdl
 
-# alu.o : alu.vhdl adder_32bit.o
-# 	${GHDL} -a -v alu.vhdl
+alu.o : alu.vhdl adder32.o
+	${GHDL} -a -v alu.vhdl
 
-# alu_tb.o : alu_tb.vhdl alu.o
-# 	${GHDL} -a -v alu_tb.vhdl
+alu_tb.o : alu_tb.vhdl alu.o
+	${GHDL} -a -v alu_tb.vhdl
 	
-# shifter.o : shifter.vhdl
-# 	${GHDL} -a -v shifter.vhdl
+shifter.o : shifter.vhdl
+	${GHDL} -a -v shifter.vhdl
 
-# shifter_tb.o : shitfter_tb.vhdl shifter.o
-# 	${GHDL} -a -v shifter_tb.vhdl
+shifter_tb.o : shitfter_tb.vhdl shifter.o
+	${GHDL} -a -v shifter_tb.vhdl
 
 adder32_tb : adder1.o adder32.o adder32_tb.o
 	${GHDL} -e -v adder32_tb

tags.ZkPwc1

@@ -1,9 +0,0 @@
-adder_4bit_ent	adder.vhdl	/^entity adder_4bit_ent is$/;"	e
-adder1bit	adder1bit.vhdl	/^ENTITY adder1bit IS$/;"	e
-adder_32bit_ent	adder_32bit.vhdl	/^ENTITY adder_32bit_ent IS$/;"	e
-adder_32bit_tb	adder_32bit_tb.vhdl	/^ENTITY adder_32bit_tb IS$/;"	e
-rand_int	adder_32bit_tb.vhdl	/^impure function rand_int(min_val, max_val : integer) return integer is$/;"	f
-adder_tb	adder_tb.vhdl	/^ENTITY adder_tb IS$/;"	e
-Alu	alu.vhdl	/^entity Alu is$/;"	e
-alu_tb	alu_tb.vhdl	/^entity alu_tb is$/;"	e
-GHDL	Makefile	/^GHDL = ghdl$/;"	m

tags.qxyh4r

@@ -1,9 +0,0 @@
-adder32_ent	adder32.vhdl	/^entity adder32_ent is$/;"	e
-adder32_tb	adder32_tb.vhdl	/^entity adder32_tb is$/;"	e
-rand_int	adder32_tb.vhdl	/^	impure function rand_int(min_val, max_val : integer) return integer is$/;"	f
-ALU	alu.vhdl	/^entity ALU is$/;"	e
-ALU_tb	alu_tb.vhdl	/^entity ALU_tb is$/;"	e
-adder1_ent	adder1.vhdl	/^entity adder1_ent is$/;"	e
-GHDL	Makefile	/^GHDL = ghdl$/;"	m
-port	adder1.h	/^	port ($/;"	p
-entity	adder1.h	/^end entity;$/;"	v

work-obj93.cf

@@ -1,4 +1,4 @@
 v 4
-file . "adder1.vhdl" "a49b2e44f386a417daff4e60add5fa1c51cd5e86" "20211027082342.208":
-  entity adder1_ent at 1( 0) + 0 on 19;
-  architecture adder1 of adder1_ent at 18( 281) + 0 on 20;
+file . "adder1.vhdl" "a49b2e44f386a417daff4e60add5fa1c51cd5e86" "20211027090039.434":
+  entity adder1_ent at 1( 0) + 0 on 21;
+  architecture adder1 of adder1_ent at 18( 281) + 0 on 22;