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Un assert de trop

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Adrien Bourmault 2021-12-10 15:49:54 +01:00
parent 9ec2a36613
commit 1beb63f3ce
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alu_tb.vhdl
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@ -280,7 +280,7 @@ begin
wait for 1 ns; wait for 1 ns;
assert false report "end_of_test" severity note; report "end_of_test" severity note;
wait; wait;
end process; end process;