From 14b2bcf4a25cd0d50651e19a40c776fe1d30ee16 Mon Sep 17 00:00:00 2001
From: shaithan <shaithan.2000@gmail.com>
Date: Thu, 9 Dec 2021 18:41:56 +0100
Subject: [PATCH] start of reg

---
 reg.vhdl | 130 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 130 insertions(+)
 create mode 100644 reg.vhdl

diff --git a/reg.vhdl b/reg.vhdl
new file mode 100644
index 0000000..5d6a40f
--- /dev/null
+++ b/reg.vhdl
@@ -0,0 +1,130 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity Reg is
+	port(
+	-- Write Port 1 prioritaire
+		wdata1			: in Std_Logic_Vector(31 downto 0);
+		wadr1			: in Std_Logic_Vector(3 downto 0);
+		wen1			: in Std_Logic;
+
+	-- Write Port 2 non prioritaire
+		wdata2			: in Std_Logic_Vector(31 downto 0);
+		wadr2			: in Std_Logic_Vector(3 downto 0);
+		wen2			: in Std_Logic;
+
+	-- Write CSPR Port
+		wcry			: in Std_Logic;
+		wzero			: in Std_Logic;
+		wneg			: in Std_Logic;
+		wovr			: in Std_Logic;
+		cspr_wb			: in Std_Logic;
+		
+	-- Read Port 1 32 bits
+		reg_rd1			: out Std_Logic_Vector(31 downto 0);
+		radr1			: in Std_Logic_Vector(3 downto 0);
+		reg_v1			: out Std_Logic;
+
+	-- Read Port 2 32 bits
+		reg_rd2			: out Std_Logic_Vector(31 downto 0);
+		radr2			: in Std_Logic_Vector(3 downto 0);
+		reg_v2			: out Std_Logic;
+
+	-- Read Port 3 32 bits
+		reg_rd3			: out Std_Logic_Vector(31 downto 0);
+		radr3			: in Std_Logic_Vector(3 downto 0);
+		reg_v3			: out Std_Logic;
+
+	-- read CSPR Port
+		reg_cry			: out Std_Logic;
+		reg_zero		: out Std_Logic;
+		reg_neg			: out Std_Logic;
+		reg_ovr			: out Std_Logic;
+
+		reg_cznv		: out Std_Logic;
+		reg_vv			: out Std_Logic;
+		
+	-- Invalidate Port 
+		inval_adr1	: in Std_Logic_Vector(3 downto 0);
+		inval1		: in Std_Logic;
+
+		inval_adr2	: in Std_Logic_Vector(3 downto 0);
+		inval2		: in Std_Logic;
+
+		inval_czn	: in Std_Logic;
+		inval_ovr	: in Std_Logic;
+
+	-- PC
+		reg_pc		: out Std_Logic_Vector(31 downto 0);
+		reg_pcv		: out Std_Logic;
+		inc_pc		: in Std_Logic;
+	
+	-- global interface
+		ck				: in Std_Logic;
+		reset_n			: in Std_Logic;
+		vdd				: in bit;
+		vss				: in bit);
+end Reg;
+
+architecture Behavior OF Reg is
+	
+	-- type representant un banc de taille 16
+	-- contenant des registres de 32 bits;
+	type lv32_array15 is array (0 to 15) of std_logic_vector(31 downto 0);
+
+	-- register_bench(0 to 14) -> registre du processeur
+	-- register_bench(15) -> pc
+	signal register_bench	: lv32_array15 := (others=>(others=>'0'));;
+	
+	-- bits de validite des registres
+	signal register_bench_v : std_logic_vector(15 downto 0) := (others=>'0');
+	signal reg_cznv_s		: std_logic := '0';
+	signal reg_vv_s			: std_logic := '0';
+
+
+begin
+	reg_logic: process(clk)
+	begin
+		if rising_edge(clk) then
+			-- reset des bits de validité
+			if (reset_n = '0') then
+				-- au reset tous les registres sont consideres comme valides
+				register_bench_v(15 donwto 0) <= (others => '1');
+
+				-- TODO : les flags sont il valide aux resets ?
+			else
+				-- gestion de la validite
+				register_bench_v(to_integer(unsigned(inval_adr1))) <= not inval1;
+				register_bench_v(to_integer(unsigned(inval_adr1))) <= not inval2;
+				
+				reg_cznv_s <= not inval_czn;
+				reg_vv_s <= not inval_ovr;
+				
+				reg_cznv <= reg_cznv_s;
+				reg_vv <= reg_vv_s;
+
+				if (reg_cznv = '0') then
+					reg_cry 	<= wcry;
+					reg_zero 	<= wzero;
+					reg_neg 	<= wneg;
+				else
+					if (reg_vv = '0') then
+						reg_ovr <= wovr;
+					end if;
+				end if;
+				
+				-- gestion de pc 
+				
+				-- write
+				
+				-- read
+				
+			
+			end if;
+		end if;
+	end process reg_logic;
+		
+
+
+end Behavior;