projet-vlsi/shifter_tb.vhdl

library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity shifter_tb is
end shifter_tb;

ARCHITECTURE Structurel OF Shifter_tb is 
signal  shift_lsl :     Std_Logic := '0';
signal  shift_lsr :     Std_Logic := '0';    
signal  shift_asr :     Std_Logic := '0';
signal  shift_ror :     Std_Logic := '0';
signal  shift_rrx :     Std_Logic := '0';    
signal  shift_val :     Std_Logic_Vector(4 downto 0);
signal  din       :     Std_Logic_Vector(31 downto 0);
signal  cin       :     Std_Logic := '0';
signal  dout      :     Std_Logic_Vector(31 downto 0);
signal  cout      :     Std_Logic;
signal  vdd       :     bit := '1';
signal  vss       :     bit := '0';

begin

shift: entity work.Shifter
port map(
            shift_lsl => shift_lsl,
            shift_lsr => shift_lsr,
            shift_asr => shift_asr,
            shift_ror => shift_ror,
            shift_rrx => shift_rrx,
            shift_val => shift_val,
            din       => din,
            cin       => cin,
            dout      => dout,
            cout      => cout,
            vdd       => vdd,
            vss       => vss
         );
process

-- Variables for the random number
variable seed1 : positive;
variable seed2 : positive;
variable x     : real;
variable y     : integer;

variable vdout : std_logic_vector(31 downto 0);
variable vcout : std_logic;

begin
    -- set vdd to 5v
    vdd <= '1';
    -- set vss to gnd
    vss <= '0';

    -- seeds for random number
    seed1 := 1;
    seed2 := 1;

    wait for 1 ns;
    report "[test_01] lsl with 32 random values";
    shift_lsl <= '1';
    la : for va in 0 to 31 loop

      uniform(seed1, seed2, x);
      y := integer(floor(x * 31.0)) + 1;

      shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));

      uniform(seed1, seed2, x);
      y := integer(floor(x * 536870911.0));
      din <= std_logic_vector(to_unsigned(y, din'length));

      if (y mod 2) = 0 then
        cin <= '1';
      else
        cin <= '0';
      end if;
      wait for 1 ns;

      --vdout := ?
      --vcout := ?
      
      report "[test_01]: din = " & integer'image(to_integer(unsigned(din)));
      report "[test_01]: shift_val = " & integer'image(to_integer(unsigned(shift_val)));

      assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
      assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
      
    end loop la;

    report "[test_01] finished";
    wait for 1 ns;
    assert false report "end_of_test" severity note;
    --  wait forever; this will finish the simulation.
    wait;
end process;

end Structurel;