projet-vlsi/adder32.vhdl

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VHDL
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2021-10-27 11:20:58 +02:00
library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------
-- adder 32 bit
-----------------------------------------------------------------
entity adder32_ent is
port (
cin : IN std_logic;
i0, i1 : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0);
cout : OUT std_logic
);
end entity;
architecture adder32 of adder32_ent is
signal co : std_logic_vector(31 downto 0);
begin
adder32_0 : entity work.adder1_ent
port map (
i0 => i0(0),
i1 => i1(0),
cin => cin,
q => q(0),
cout => co(0)
);
loop_29: for i in 1 to 30 generate
adder32_n : entity work.adder1_ent
port map (
i0 => i0(i),
i1 => i1(i),
cin => co(i-1),
q => q(i),
cout => co(i)
);
end generate loop_29;
adder32_31 : entity work.adder1_ent
port map (
i0 => i0(31),
i1 => i1(31),
cin => co(30),
q => q(31),
cout => cout
);
end adder32;