projet-vlsi/adder1.vhdl

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VHDL
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2021-10-27 11:20:58 +02:00
library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-- ADDER 1 BIT
----------------------------------------------------------------
entity adder1_ent is
port (
i0, i1, cin : IN std_logic;
q, cout : OUT std_logic
);
end entity;
architecture adder1 of adder1_ent is
begin
q <= i0 xor i1 xor cin;
cout <= (i0 and i1) or (i0 and cin) or (i1 and cin);
end adder1;