projet-vlsi/adder_tb.vhdl

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VHDL
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2021-10-26 19:06:02 +02:00
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY adder_tb IS
END adder_tb;
ARCHITECTURE Structurel OF adder_tb is
COMPONENT adder
PORT (
i0, i1 : IN std_logic_vector(3 downto 0);
q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL i0, i1, q : std_logic_vector(3 downto 0);
signal vadd : std_logic_vector(3 downto 0);
BEGIN
adder_0: entity work.adder_4bit_ent
PORT MAP( i0 => i0,
i1 => i1,
q => q);
process
begin
loop_i0: for va in 0 to 15 loop
loop_i1: for vb in 0 to 15 loop
i0 <= std_logic_vector(to_unsigned(va, 4));
i1 <= std_logic_vector(to_unsigned(vb, 4));
vadd <= std_logic_vector(to_unsigned(va+vb, 4));
REPORT "i0 : " & integer'image(to_integer(unsigned(i0)))
& " + i1 : "
& integer'image(to_integer(unsigned(i1)))
& " = "
& integer'image(to_integer(unsigned(q)));
ASSERT vadd = q REPORT "ERROR not equal !" SEVERITY ERROR;
wait for 2 fs;
end loop loop_i1;
end loop loop_i0;
WAIT;
end process;
END Structurel;