78 lines
1.8 KiB
VHDL
78 lines
1.8 KiB
VHDL
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LIBRARY ieee;
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use ieee.math_real.all;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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---
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ENTITY adder_32bit_tb IS
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END adder_32bit_tb;
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---
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ARCHITECTURE Structurel OF adder_32bit_tb is
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COMPONENT adder
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PORT (
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cin : IN std_logic;
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i0, i1 : IN std_logic_vector(31 downto 0);
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q : OUT std_logic_vector(31 downto 0);
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cout : OUT std_logic
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);
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END COMPONENT;
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SIGNAL cout, cin : std_logic;
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SIGNAL i0, i1, q_32 : std_logic_vector(31 downto 0);
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signal vadd : std_logic_vector(31 downto 0);
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impure function rand_int(min_val, max_val : integer) return integer is
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variable r : real;
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variable seed1, seed2 : integer := 998;
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begin
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uniform(seed1, seed2, r);
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return integer(
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round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
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end function;
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BEGIN
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adder_0: entity work.adder_32bit_ent
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PORT MAP(
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cin => cin,
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i0 => i0,
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i1 => i1,
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q => q_32,
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cout => cout
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);
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process
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variable rva, rvb : integer;
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begin
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cin <= '0';
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loop_i0: for va in 0 to 15 loop
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loop_i1: for vb in 0 to 15 loop
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rva := rand_int(-200, 200);
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rvb := rand_int(-200, 200);
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i0 <= std_logic_vector(to_unsigned(va, 32));
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i1 <= std_logic_vector(to_unsigned(vb, 32));
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vadd <= std_logic_vector(to_unsigned(va+vb, 32));
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wait for 2 fs;
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REPORT "i0 : " & integer'image(to_integer(unsigned(i0)))
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& " + i1 : "
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& integer'image(to_integer(unsigned(i1)))
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& " = "
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& integer'image(to_integer(unsigned(q_32)))
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& " ( vadd = "
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& integer'image(to_integer(unsigned(vadd)))
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& " ) ";
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ASSERT vadd = q_32 REPORT "ERROR not equal !" SEVERITY ERROR;
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end loop loop_i1;
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end loop loop_i0;
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WAIT;
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end process;
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END Structurel;
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