projet-vlsi/adder_32bit_tb.vhdl

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VHDL
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2021-10-26 19:06:02 +02:00
LIBRARY ieee;
use ieee.math_real.all;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---
ENTITY adder_32bit_tb IS
END adder_32bit_tb;
---
ARCHITECTURE Structurel OF adder_32bit_tb is
COMPONENT adder
PORT (
cin : IN std_logic;
i0, i1 : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0);
cout : OUT std_logic
);
END COMPONENT;
SIGNAL cout, cin : std_logic;
SIGNAL i0, i1, q_32 : std_logic_vector(31 downto 0);
signal vadd : std_logic_vector(31 downto 0);
impure function rand_int(min_val, max_val : integer) return integer is
variable r : real;
variable seed1, seed2 : integer := 998;
begin
uniform(seed1, seed2, r);
return integer(
round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
end function;
BEGIN
adder_0: entity work.adder_32bit_ent
PORT MAP(
cin => cin,
i0 => i0,
i1 => i1,
q => q_32,
cout => cout
);
process
variable rva, rvb : integer;
begin
cin <= '0';
loop_i0: for va in 0 to 15 loop
loop_i1: for vb in 0 to 15 loop
rva := rand_int(-200, 200);
rvb := rand_int(-200, 200);
i0 <= std_logic_vector(to_unsigned(va, 32));
i1 <= std_logic_vector(to_unsigned(vb, 32));
vadd <= std_logic_vector(to_unsigned(va+vb, 32));
wait for 2 fs;
REPORT "i0 : " & integer'image(to_integer(unsigned(i0)))
& " + i1 : "
& integer'image(to_integer(unsigned(i1)))
& " = "
& integer'image(to_integer(unsigned(q_32)))
& " ( vadd = "
& integer'image(to_integer(unsigned(vadd)))
& " ) ";
ASSERT vadd = q_32 REPORT "ERROR not equal !" SEVERITY ERROR;
end loop loop_i1;
end loop loop_i0;
WAIT;
end process;
END Structurel;