46 lines
1.0 KiB
VHDL
46 lines
1.0 KiB
VHDL
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY adder_tb IS
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END adder_tb;
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ARCHITECTURE Structurel OF adder_tb is
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COMPONENT adder
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PORT (
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i0, i1 : IN std_logic_vector(3 downto 0);
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q : OUT std_logic_vector(3 downto 0)
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);
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END COMPONENT;
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SIGNAL i0, i1, q : std_logic_vector(3 downto 0);
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signal vadd : std_logic_vector(3 downto 0);
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BEGIN
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adder_0: entity work.adder_4bit_ent
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PORT MAP( i0 => i0,
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i1 => i1,
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q => q);
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process
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begin
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loop_i0: for va in 0 to 15 loop
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loop_i1: for vb in 0 to 15 loop
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i0 <= std_logic_vector(to_unsigned(va, 4));
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i1 <= std_logic_vector(to_unsigned(vb, 4));
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vadd <= std_logic_vector(to_unsigned(va+vb, 4));
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REPORT "i0 : " & integer'image(to_integer(unsigned(i0)))
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& " + i1 : "
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& integer'image(to_integer(unsigned(i1)))
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& " = "
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& integer'image(to_integer(unsigned(q)));
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ASSERT vadd = q REPORT "ERROR not equal !" SEVERITY ERROR;
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wait for 2 fs;
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end loop loop_i1;
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end loop loop_i0;
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WAIT;
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end process;
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END Structurel;
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