21 lines
492 B
VHDL
21 lines
492 B
VHDL
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library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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-- ADDER 1 BIT
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----------------------------------------------------------------
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ENTITY adder1bit IS
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PORT (
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i0, i1, cin : IN std_logic;
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q, cout : OUT std_logic
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);
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END ENTITY;
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-----------------------------------------------------------------
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ARCHITECTURE full_adder_1bit OF adder1bit IS
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BEGIN
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q <= i0 XOR i1 XOR cin;
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cout <= (i0 and i1) or (i0 and cin) or (i1 and cin);
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END full_adder_1bit;
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