49 lines
979 B
VHDL
49 lines
979 B
VHDL
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library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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--use work.adder1bit.all;
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-----------------------------------------------------------------
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-- ADDER 4 BIT
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-----------------------------------------------------------------
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ENTITY adder_4bit_ent IS
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PORT (
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i0, i1 : IN std_logic_vector(3 downto 0);
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q : OUT std_logic_vector(3 downto 0)
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);
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END ENTITY;
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-----------------------------------------------------------------
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ARCHITECTURE adder_4bit OF adder_4bit_ent IS
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--COMPONENT adder1bit IS
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--PORT (
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-- i0, i1, cin : IN std_logic;
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-- q, cout : OUT std_logic
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--);
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--END COMPONENT;
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SIGNAL co : std_logic_vector(3 downto 0);
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BEGIN
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adder0 : entity work.adder1bit
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PORT MAP (
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i0 => i0(0),
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i1 => i1(0),
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cin => '0',
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q => q(0),
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cout => co(0)
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);
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loop_3: for i in 1 to 3 generate
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adderN : entity work.adder1bit
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PORT MAP (
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i0 => i0(i),
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i1 => i1(i),
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cin => co(i-1),
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q => q(i),
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cout => co(i)
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);
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END GENERATE loop_3;
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END adder_4bit;
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