projet-vlsi/Makefile

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Makefile
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2021-10-26 19:06:02 +02:00
GHDL = ghdl
all : sim
adder1bit.o : adder1bit.vhdl
${GHDL} -a -v adder1bit.vhdl
adder_32bit.o : adder_32bit.vhdl adder1bit.o
${GHDL} -a -v adder_32bit.vhdl
adder_32bit_tb.o : adder_32bit_tb.vhdl adder_32bit.o
${GHDL} -a -v adder_32bit_tb.vhdl
adder_32bit_tb : adder_32bit_tb.o
${GHDL} -e -v adder_32bit_tb
alu.o : alu.vhdl adder_32bit.o
${GHDL} -a -v alu.vhdl
alu_tb.o : alu_tb.vhdl alu.o
${GHDL} -a -v alu_tb.vhdl
alu_tb : alu.o alu_tb.o
${GHDL} -e -v alu_tb
shifter.o : shifter.vhdl
${GHDL} -a -v shifter.vhdl
shifter_tb.o : shitfter_tb.vhdl shifter.o
${GHDL} -a -v shifter_tb.vhdl
shifter_tb : shitfter_tb.o
${GHDL} -e -v shifter_tb
sim_adder_32bit : adder_32bit_tb
${GHDL} -r adder_32bit_tb --vcd=adder_32bit.vcd
sim : alu_tb
${GHDL} -r alu_tb --vcd=alu.vcd
clean :
-rm *.o work-obj93.cf *_tb *.vcd