50 lines
1.3 KiB
VHDL
50 lines
1.3 KiB
VHDL
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-- Company: UPMC
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-- Designed by: E.PIMOR S.HAMOUM, Spring 2017
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-- Revision by: J.DENOULET, Summer 2017
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--
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-- Module Name: CLK_DIV - Behavioral
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-- Project Name: Centrale DCC
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-- Target Devices: NEXYS 4 DDR
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--
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-- Diviseur d'Horloge: 100 MHé --> 1 MHz
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity CLK_DIV is
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Port ( Reset : in STD_LOGIC; -- Reset Asynchrone
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Clk_In : in STD_LOGIC; -- Horloge 100 MHz de la carte Nexys
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Clk_Out : out STD_LOGIC); -- Horloge 1 MHz de sortie
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end CLK_DIV;
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architecture Behavioral of CLK_DIV is
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signal Div : INTEGER range 0 to 49; -- Compteur de cycles d'horloge
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signal Clk_Temp : STD_LOGIC; -- Signal temporaire
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begin
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Clk_Out <= Clk_Temp; -- Affectation du Port de Sortie
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process (Clk_In, Reset)
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begin
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-- Reset Asynchrone
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if Reset = '1' then
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Clk_Temp <= '0';
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-- A Chaque Front d'Horloge
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elsif rising_edge (Clk_In) then
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Div <= Div + 1; -- Incrémentation du Compteur
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if Div = 49 then -- Inversion du Signal d'Horloge Tous les 50 Cycles
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Div <= 0;
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Clk_Temp <= not Clk_Temp;
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end if;
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end if;
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end process;
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end Behavioral;
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