64 lines
1.6 KiB
VHDL
64 lines
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity dcc_bit_1_tb is
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end dcc_bit_1_tb;
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architecture tb of dcc_bit_1_tb is
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constant ClockPeriod1 : time := 1 us;
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constant ClockPeriod100 : time := 10 ns;
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signal reset : std_logic := '1';
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signal go : std_logic := '0'; --inputs
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signal clk_100MHz : std_logic := '0';
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signal clk_1MHz : std_logic := '0'; --clocks
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signal fin, dcc_1 : std_logic; --outputs
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begin
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uut : entity work.DCC_Bit_1 port map(
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reset => reset,
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clk_100MHz => clk_100Mhz,
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clk_1MHz => clk_1MHz,
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go => go,
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fin => fin,
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dcc_1 => dcc_1
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);
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clk_100MHz <= not clk_100MHz after ClockPeriod100 / 2;
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clk_1MHz <= not clk_1MHz after ClockPeriod1 / 2;
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process
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begin
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reset <= '0';
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wait for 20 ns;
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for i in 0 to 50 loop
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go <= '1';
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wait until rising_edge(clk_100MHz);
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go <= '0';
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assert(dcc_1 = '0') report "dcc_1 invalide avant 58us, est à 1 (test"
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& integer'image(i) & ")";
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wait until rising_edge(dcc_1) for 58 us;
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assert(dcc_1 = '1') report "dcc_1 invalide après 58us, est à 0 (test"
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& integer'image(i) & ")";
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wait until falling_edge(dcc_1) for 58 us;
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assert(dcc_1 = '0') report "dcc_1 invalide après 58us * 2, est à 1 (test"
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& integer'image(i) & ")";
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--assert(false) report "test" & integer'image(i) severity warning;
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assert(fin = '1') report "fin invalide, est à 0";
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wait until rising_edge(clk_1MHz);
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end loop;
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assert(false) report "Test DCC_Bit_1 terminé" severity warning;
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wait;
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end process;
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end tb;
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