88 lines
1.4 KiB
VHDL
88 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity dcc_bit_1 is
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port(
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reset : in std_logic;
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clk_100MHz : in std_logic;
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clk_1MHz : in std_logic;
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go : in std_logic;
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fin : out std_logic;
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dcc_1 : out std_logic
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);
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end dcc_bit_1;
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architecture behaviour of dcc_bit_1 is
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type state is (idle, out_0, out_1);
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signal cs, fs : state;
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signal inc_cpt : std_logic;
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signal cpt : integer range 0 to 116;
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signal out_value : std_logic := '0';
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begin
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dcc_1 <= out_value;
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--MAE
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process(clk_100MHz, reset)
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begin
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if reset = '1' then
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fs <= idle;
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elsif rising_edge(clk_100MHz) then
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if cs = idle then
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fin <= '0';
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out_value <= '0';
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if go = '1' then
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inc_cpt <= '1';
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fs <= out_0;
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end if;
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elsif cs = out_0 then
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out_value <= '0';
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if cpt >= 57 then
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fs <= out_1;
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end if;
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elsif cs = out_1 then
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out_value <= '1';
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if cpt >= 115 then
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fs <= idle;
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out_value <= '0';
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fin <= '1';
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inc_cpt <= '0';
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end if;
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end if;
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cs <= fs;
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end if;
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end process;
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--Compteur de Temporisation
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process(clk_1MHz, reset)
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begin
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if reset = '1' then
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cpt <= 0;
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elsif rising_edge(clk_1MHz) then
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if inc_cpt = '1' then
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cpt <= cpt + 1;
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else
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cpt <= 0;
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end if;
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end if;
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end process;
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end behaviour;
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