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library ieee;
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use ieee.std_logic_1164.all;
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entity registre_dcc_tb is
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end registre_dcc_tb;
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architecture tb of registre_dcc_tb is
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signal trame_dcc : std_logic_vector(50 donwto 0);
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signal clk, reset, shift, load : std_logic;
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signal sout : std_logic;
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begin
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end tb; |