46 lines
819 B
VHDL
46 lines
819 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity registre_dcc is
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port(
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trame_dcc : in std_logic_vector(50 downto 0);
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clk : in std_logic;
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reset : in std_logic;
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shift : in std_logic;
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load : in std_logic;
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sout : out std_logic
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);
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end registre_dcc;
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architecture behaviour of registre_dcc is
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signal sr : std_logic_vector(50 downto 0);
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signal lc_shift : std_logic := '0';
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begin
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process(clk, reset, shift)
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begin
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if reset = '1' then
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sr <= ( others => '0' );
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elsif rising_edge(clk) then
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if load = '1' then
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sr <= trame_dcc;
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elsif shift = '1' and lc_shift = '0' then
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sr <= sr(49 downto 0) & '0';
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lc_shift <= '1';
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elsif shift = '0' then
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lc_shift <= '0';
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end if;
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end if;
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end process;
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sout <= sr(50);
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end behaviour;
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