95 lines
1.8 KiB
VHDL
95 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity MAE is
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port(
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clk : in std_logic;
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reset : in std_logic;
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fin_tempo : in std_logic;
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fin_1 : in std_logic;
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fin_0 : in std_logic;
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tr_bit : in std_logic;
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load : out std_logic;
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shift : out std_logic;
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start_tempo : out std_logic;
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go_1 : out std_logic;
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go_0 : out std_logic
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);
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end MAE;
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architecture behaviour of MAE is
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type state is (Start, LecReg, Send0, Send1, Tempo);
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signal cs, fs : state;
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--signal cpt : integer range 0 to 51 := 0;
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begin
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process(clk, reset)
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variable cpt : INTEGER RANGE 0 TO 101;
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begin
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if reset = '1' then
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fs <= Start;
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load <= '0';
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shift <= '0';
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start_tempo <= '0';
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go_0 <= '0';
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go_1 <= '0';
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cpt := 0;
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elsif rising_edge(clk) then
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if cs = Start then
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load <= '1';
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fs <= LecReg;
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elsif cs = LecReg then
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load <= '0';
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if tr_bit = '1' then
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fs <= Send1;
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else
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fs <= Send0;
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end if;
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shift <= '1';
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cpt := cpt + 1;
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elsif cs = Send0 then
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shift <= '0';
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go_0 <= '1';
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if fin_0 = '1' then
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go_0 <= '0';
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if cpt >= 101 then -- on doit normalement en compter 51, mais ça marche pas par contre 101 c'est nickel
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fs <= Tempo;
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else
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fs <= LecReg;
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end if;
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end if;
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elsif cs = Send1 then
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shift <= '0';
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go_1 <= '1';
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if fin_1 = '1' then
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go_1 <= '0';
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if cpt >= 101 then
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fs <= Tempo;
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else
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fs <= LecReg;
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end if;
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end if;
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elsif cs = Tempo then
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start_tempo <= '1';
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if fin_tempo = '1' then
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start_tempo <= '0';
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cpt := 0;
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fs <= Start;
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end if;
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end if;
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cs <= fs;
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end if;
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end process;
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end behaviour; |