25 lines
468 B
VHDL
25 lines
468 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity Diviseur_Horloge_TB is
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end Diviseur_Horloge_TB;
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architecture tb of Diviseur_Horloge_TB is
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constant t : time:= 10 ns;
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signal reset, clk_in : std_logic;
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signal clk_out : std_logic;
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begin
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uut : entity work.diviseur_horloge
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port map( reset => reset, clk_in => clk_in, clk_out => clk_out);
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process
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begin
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clk <= '0';
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wait for T/2;
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clk <= '1';
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wait for T/2;
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end process;
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end; |