projet-fpga/Diviseur_Horloge_TB.vhd

25 lines
468 B
VHDL

library ieee;
use ieee.std_logic_1164.all;
entity Diviseur_Horloge_TB is
end Diviseur_Horloge_TB;
architecture tb of Diviseur_Horloge_TB is
constant t : time:= 10 ns;
signal reset, clk_in : std_logic;
signal clk_out : std_logic;
begin
uut : entity work.diviseur_horloge
port map( reset => reset, clk_in => clk_in, clk_out => clk_out);
process
begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process;
end;