36 lines
726 B
VHDL
36 lines
726 B
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
|
|
entity Compteur_Tempo_TB is
|
|
end Compteur_Tempo_TB;
|
|
|
|
architecture tb of Compteur_Tempo_TB is
|
|
constant T1 : time := 10 ns;
|
|
constant T2 : time := 1000 ns;
|
|
signal clk, reset, clk1m, start_tempo : std_logic;
|
|
signal fin_tempo : std_logic;
|
|
|
|
begin
|
|
uut: entity work.compteur_tempo
|
|
port map( clk => clk, reset => reset, clk1m => clk1m, start_tempo => start_tempo, fin_tempo => fin_tempo);
|
|
|
|
process
|
|
begin
|
|
clk <= '0';
|
|
wait for T1/2;
|
|
clk <= '1';
|
|
wait for T1/2;
|
|
end process;
|
|
|
|
process
|
|
begin
|
|
clk1m <= '0';
|
|
wait for T2/2;
|
|
clk1m <= '1';
|
|
wait for T2/2;
|
|
end process;
|
|
|
|
reset <= '1', '0' after T/2;
|
|
start_tempo <= '1' after T/2;
|
|
|
|
end tb; |