library ieee;
use ieee.std_logic_1164.all;

entity top_dcc is
	port(
		Clk : in std_logic;
		reset : in std_logic;
		interrupteur : in std_logic_vector(7 downto 0);
		sortie_dcc : out std_logic
	);
end top_dcc;

architecture structural of top_dcc is

signal trame_dcc : std_logic_vector(50 downto 0);

signal reg_shift : std_logic;
signal reg_load : std_logic;
signal reg_out : std_logic;

signal start_tempo : std_logic;
signal fin_tempo : std_logic;

signal go_0 : std_logic;
signal fin_0 : std_logic;
signal dcc_0 : std_logic;

signal go_1 : std_logic;
signal fin_1 : std_logic;
signal dcc_1 : std_logic;


signal clk_1MHz : std_logic;
	
begin
	cp_tempo : entity work.Compteur_Tempo port map (clk => clk, reset => reset, Clk1M => clk_1MHz, 
	                                               start_tempo => start_tempo, fin_tempo => fin_tempo);

	dcc_bit_0 : entity work.DCC_Bit_0 port map (reset => reset, clk_100MHz => clk, clk_1MHz => clk_1MHz, 
						go => go_0, fin => fin_0, dcc_0 => dcc_0);

	dcc_bit_1 : entity work.DCC_Bit_1 port map (reset => reset, clk_100MHz => clk, clk_1MHz => clk_1MHz,
						 go => go_1, fin => fin_1, dcc_1 => dcc_1);

	diviseur_horloge : entity work.CLK_DIV port map (reset => reset, clk_in => clk, clk_out => clk_1MHz);

	mae : entity work.MAE port map(clk => clk, reset => reset, fin_tempo => fin_tempo, fin_1 => fin_1,
					fin_0 => fin_0, tr_bit => reg_out, load => reg_load, shift => reg_shift,
					start_tempo => start_tempo, go_1 => go_1, go_0 => go_0);

	registre_dcc : entity work.Registre_DCC port map (trame_dcc => trame_dcc, clk => clk, 
							reset => reset, shift => reg_shift, load => reg_load,
							sout => reg_out);

	gen_trame : entity work.dcc_frame_generator port map(interrupteur => interrupteur, Trame_DCC => trame_dcc);

	sortie_dcc <= dcc_1 or dcc_0;

end structural;