library ieee;
use ieee.std_logic_1164.all;

entity registre_dcc is
	port(
		trame_dcc : in std_logic_vector(50 downto 0);
		clk : in std_logic;
		reset : in std_logic;
		shift : in std_logic;
		load : in std_logic;
		sout : out std_logic

	);

end registre_dcc;

architecture  behaviour of registre_dcc is
	signal sr : std_logic_vector(50 downto 0);
	signal lc_shift : std_logic := '0';

begin
	process(clk, reset, shift)
	begin
		if reset = '1' then 
			sr <= ( others => '0' );

		elsif rising_edge(clk) then
			if load = '1' then
				sr <= trame_dcc;

			elsif shift = '1' and lc_shift = '0' then
				sr <= sr(49 downto 0) & '0';
				lc_shift <= '1';

			elsif shift = '0' then
				lc_shift <= '0';

			end if;

		end if;

	end process;
	sout <= sr(50); 

end behaviour;