library ieee;
use ieee.std_logic_1164.all;

entity dcc_bit_1_tb is
end dcc_bit_1_tb;


architecture tb of dcc_bit_1_tb is

	constant ClockPeriod1 : time := 1 us;
	constant ClockPeriod100 : time := 10 ns;

	signal reset : std_logic := '1';
	signal go : std_logic :=  '0'; --inputs
	signal clk_100MHz : std_logic := '0';
	signal clk_1MHz : std_logic := '0'; --clocks
	signal fin, dcc_1 : std_logic; --outputs

begin
	uut : entity work.DCC_Bit_1 port map(
						reset => reset,
						clk_100MHz => clk_100Mhz,
						clk_1MHz => clk_1MHz,
						go => go,
						fin => fin,
						dcc_1 => dcc_1
					);

	clk_100MHz <= not clk_100MHz after ClockPeriod100 / 2;
	clk_1MHz <= not clk_1MHz after ClockPeriod1 / 2;
	
	process
	begin
		reset <= '0';
	
		wait for 20 ns;
		go <= '1';
		wait for 20 ns;
		go <= '0';
		wait for 200 us;
		go <= '1';
		wait for 20 us;
		go <= '0';
		wait;	
	end process;
	
end tb;