diff --git a/DCC_Bit_1.vhd b/DCC_Bit_1.vhd
index b87461f..f750158 100644
--- a/DCC_Bit_1.vhd
+++ b/DCC_Bit_1.vhd
@@ -17,7 +17,7 @@ architecture behaviour of dcc_bit_1 is
 	type state is (idle, out_0, out_1);
 	signal cs, fs : state;
 	signal inc_cpt : std_logic;
-	signal cpt : integer range 0 to 126;
+	signal cpt : integer range 0 to 116;
 	signal out_value : std_logic := '0';
 begin
 	dcc_1 <= out_value;
@@ -25,7 +25,9 @@ begin
 	--MAE
 	process(clk_100MHz, reset)
 	begin
-		if reset = '1' then fs <= idle;
+		if reset = '1' then 
+			fs <= idle;
+
 		elsif rising_edge(clk_100MHz) then
 
 			if cs = idle then
@@ -42,15 +44,17 @@ begin
 
 				out_value <= '0';
 
-				if cpt > 57 then fs <= out_1;
+				if cpt >= 57 then 
+					fs <= out_1;
 				end if;
 
 			elsif cs = out_1 then 
 
 				out_value <= '1';
 
-				if cpt > 125 then
+				if cpt >= 115 then
 					fs <= idle;
+					out_value <= '0';
 					fin <= '1';
 					inc_cpt <= '0';
 				end if;			
@@ -58,7 +62,7 @@ begin
 			end if;
 			cs <= fs;
 		end if;
-				
+
 	end process;
 
 	--Compteur de Temporisation
@@ -72,10 +76,12 @@ begin
         
 			if inc_cpt = '1' then
 				cpt <= cpt + 1;
+			else
+				cpt <= 0;
 			end if;
         
 		end if;
 	end process;
 
 	
-end behaviour;
\ No newline at end of file
+end behaviour;
diff --git a/DCC_Bit_1_TB.vhd b/DCC_Bit_1_TB.vhd
index ad772a4..2485156 100644
--- a/DCC_Bit_1_TB.vhd
+++ b/DCC_Bit_1_TB.vhd
@@ -32,12 +32,32 @@ begin
 	process
 	begin
 		reset <= '0';
-		
 		wait for 20 ns;
-		go <= '1';
-		wait for 30 ns;
-		go <= '0';
-		wait;	
+		
+		for i in 0 to 50 loop
+			go <= '1';
+			wait until rising_edge(clk_100MHz);
+			go <= '0';
+
+			assert(dcc_1 = '0') report "dcc_1 invalide avant 58us, est à 1 (test" 
+				& integer'image(i) & ")";
+			wait until rising_edge(dcc_1) for 58 us;
+			assert(dcc_1 = '1') report "dcc_1 invalide après 58us, est à 0 (test"
+				& integer'image(i) & ")";
+			wait until falling_edge(dcc_1) for 58 us;
+			assert(dcc_1 = '0') report "dcc_1 invalide après 58us * 2, est à 1 (test"
+				& integer'image(i) & ")";
+
+			--assert(false) report "test" & integer'image(i) severity warning;
+			assert(fin = '1') report "fin invalide, est à 0";
+			
+			wait until rising_edge(clk_1MHz);
+
+		end loop;
+		
+		assert(false) report "Test DCC_Bit_1 terminé" severity warning;
+		
+		wait;
 	end process;
 	
-end tb;
\ No newline at end of file
+end tb;