projet-fpga/Registre_DCC_TB.vhd

library ieee;
use ieee.std_logic_1164.all;

entity registre_dcc_tb is
end registre_dcc_tb;

architecture tb of registre_dcc_tb is
	signal trame_dcc : std_logic_vector(50 donwto 0);
	signal clk, reset, shift, load : std_logic;
	signal sout : std_logic;
begin
end tb;