library ieee;
use ieee.std_logic_1164.all;

entity top_dcc_tb is
end top_dcc_tb;

architecture tb of top_dcc_tb is 

constant period : time := 10 ns;

signal clk : std_logic;
signal reset : std_logic;
signal interrupteur : std_logic_vector(7 downto 0);
signal dcc_out : std_logic;

begin
    uut : entity work.top_dcc port map(clk => clk, reset => reset, 
                                       interrupteur => interrupteur,
                                       sortie_dcc => dcc_out);
    
    process
    begin
        clk <= '0';
        wait for period/2;
        clk <= '1';
        wait for period/2;
    end process;
    
    reset <= '1', '0' after 1 us;
    
    interrupteur <= ( '1', others => '0'), (others => '0') after 12 ms;
        

end tb; 