TME2 MOCCA - clicker le plus cher
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include help.mk
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ALLIANCE=/users/outil/alliance/alliance/Linux.el7_64/install
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CMOS = $(ALLIANCE)/etc/cmos.rds
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S130 = sky130_lsx.rds
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SLIB = $(ALLIANCE)/cells/sxlib
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PLIB = $(ALLIANCE)/cells/pxlib
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VASY = export MBK_WORK_LIB=.; vasy
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XPAT = export MBK_WORK_LIB=.; xpat
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ASIM = export MBK_WORK_LIB=.; MBK_CATA_LIB=$(SLIB); asimut
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BOOM = export MBK_WORK_LIB=.; boom
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BOOG = export MBK_WORK_LIB=. MBK_TARGET_LIB=$(SLIB); MBK_OUT_LO=vst; boog
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XSCH = export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB); xsch
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PLACE= export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB); ocp
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ROUTE= export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB); nero
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RING = export MBK_WORK_LIB=. MBK_CATA_LIB=$(PLIB); ring
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GRAAL= export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB); graal
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DRUC = export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB) RDS_TECHNO_NAME=$(CMOS); druc
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DREAL= export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB) RDS_TECHNO_NAME=$(S130); dreal
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S2R = export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB) RDS_TECHNO_NAME=$(S130); s2r
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EXTC = export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB) RDS_TECHNO_NAME=$(CMOS) MBK_OUT_LO=vst;\
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cougar -c
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EXTT = export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB) RDS_TECHNO_NAME=$(CMOS) MBK_OUT_LO=spi;\
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cougar -t
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#% Configuration
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MODEL ?= clicker#% Nom du modèle à créer
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VERBOSE ?= 0
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## Tout en une fois
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all: s2r ## Lance toutes les étapes de conceptions
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## Etapes
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## > validation
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vasy: ## Genere le vbe à partir du vhd
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$(VASY) -a -I vhd -p -o $(MODEL) $(MODEL)_v
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simul_pat: vasy ## Simule un jeu de patterns écrit à la main
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$(ASIM) -b $(MODEL)_v patterns/$(MODEL) $(MODEL)_res
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@if [[ "$(VERBOSE)" == "1" ]]; then $(XPAT) -l $(MODEL)_res; fi
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simul_gpat: vasy ## Simule un jeu de patterns générés
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export MODEL=$(MODEL) CYCLES=50 TYPE=BEH; genpat patterns/$(MODEL)
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$(ASIM) -b $(MODEL)_v $(MODEL)_gen $(MODEL)_gres
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@if [[ "$(VERBOSE)" == "1" ]]; then $(XPAT) -l $(MODEL)_gres; fi
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## > Synthèse
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synth: simul_pat ## Synthétise pour produire la netlist de porte
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$(BOOM) $(MODEL)_v $(MODEL)_o
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$(BOOG) $(MODEL)_o $(MODEL)_o
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@if [[ "$(VERBOSE)" == "1" ]]; then $$(XSCH) -l $(MODEL)_o; fi
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place: synth ## Place les cellules du core
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$(PLACE) -margin 0.3 -mdl 10 -ring $(MODEL)_o $(MODEL)_p
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@if [[ "$(VERBOSE)" == "1" ]]; then $(GRAAL) -l $(MODEL)_p; fi
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route: place ## Route le core
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$(ROUTE) -p $(MODEL)_p $(MODEL)_o $(MODEL)_o
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@if [[ "$(VERBOSE)" == "1" ]]; then $(GRAAL) -l $(MODEL)_o; fi
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ring: route ## Route le core et les plots
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cpp $(MODEL).h -DCORE=$(MODEL)_o | grep -v "^#" > $(MODEL)_chip.vst
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cpp $(MODEL).h -DPLOT | grep -v "^#" > $(MODEL)_chip.rin
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$(RING) $(MODEL)_chip $(MODEL)_chip
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@if [[ "$(VERBOSE)" == "1" ]]; then $(GRAAL) -l $(MODEL)_chip; fi
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s2r: druc ## Génère le format CIF
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$(S2R) -tv $(MODEL)_chip
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$(DREAL) -l $(MODEL)_chip
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@if [[ "$(VERBOSE)" == "1" ]]; then $(DREAL) -l $(MODEL)_chip; fi
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## > Vérification
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druc: ring ## Vérifie les règles de dessin de tous le circuit
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$(DRUC) $(MODEL)_o
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cougar_cell: s2r ## Extraction du coeur jusqu'aux cellules
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$(EXTC) -c $(MODEL)_o $(MODEL)_x
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cougar_tran: s2r ## Extraction du coeur jusqu'aux transistors
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$(EXTT) -t $(MODEL)_o $(MODEL)_x
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resimul_pat: cougar_cell ## Simule un jeu de patterns générés
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$(ASIM) -zd $(MODEL)_x patterns/$(MODEL)x $(MODEL)_resx
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@if [[ "$(VERBOSE)" == "1" ]]; then $(XPAT) -l $(MODEL)_resx; fi
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resimul_gpat: cougar_cell ## Simule un jeu de patterns générés
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export MODEL=$(MODEL) CYCLES=50 TYPE=NET; genpat patterns/$(MODEL)
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$(ASIM) -zd $(MODEL)_x $(MODEL)_genx $(MODEL)_gresx
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@if [[ "$(VERBOSE)" == "1" ]]; then $(XPAT) -l $(MODEL)_gresx; fi
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## Divers
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clean: ## Efface tous les fichiers intermédiaires
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rm -f $(MODEL)_*.* Makefile.*
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@ -0,0 +1,101 @@
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include help.mk
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ALLIANCE=/users/outil/alliance/alliance/Linux.el7_64/install
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CMOS = $(ALLIANCE)/etc/cmos.rds
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S130 = sky130_lsx.rds
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SLIB = $(ALLIANCE)/cells/sxlib
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PLIB = $(ALLIANCE)/cells/pxlib
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VASY = export MBK_WORK_LIB=.; vasy
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XPAT = export MBK_WORK_LIB=.; xpat
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ASIM = export MBK_WORK_LIB=.; MBK_CATA_LIB=$(SLIB); asimut
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BOOM = export MBK_WORK_LIB=.; boom
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BOOG = export MBK_WORK_LIB=. MBK_TARGET_LIB=$(SLIB); MBK_OUT_LO=vst; boog
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XSCH = export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB); xsch
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PLACE= export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB); ocp
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ROUTE= export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB); nero
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RING = export MBK_WORK_LIB=. MBK_CATA_LIB=$(PLIB); ring
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GRAAL= export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB); graal
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DRUC = export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB) RDS_TECHNO_NAME=$(CMOS); druc
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DREAL= export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB) RDS_TECHNO_NAME=$(S130); dreal
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S2R = export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB) RDS_TECHNO_NAME=$(S130); s2r
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EXTC = export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB) RDS_TECHNO_NAME=$(CMOS) MBK_OUT_LO=vst;\
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cougar -c
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EXTT = export MBK_WORK_LIB=. MBK_CATA_LIB=$(SLIB):$(PLIB) RDS_TECHNO_NAME=$(CMOS) MBK_OUT_LO=spi;\
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cougar -t
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#% Configuration
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MODEL ?= clicker#% Nom du modèle à créer
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VERBOSE ?= 0
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## Tout en une fois
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all: s2r ## Lance toutes les étapes de conceptions
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## Etapes
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## > validation
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vasy: ## Genere le vbe à partir du vhd
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$(VASY) -a -I vhd -p -o $(MODEL) $(MODEL)_v
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simul_pat: vasy ## Simule un jeu de patterns écrit à la main
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$(ASIM) -b $(MODEL)_v patterns/$(MODEL) $(MODEL)_res
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@if [[ "$(VERBOSE)" == "1" ]]; then $(XPAT) -l $(MODEL)_res; fi
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simul_gpat: vasy ## Simule un jeu de patterns générés
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export MODEL=$(MODEL) CYCLES=50 TYPE=BEH; genpat patterns/$(MODEL)
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$(ASIM) -b $(MODEL)_v $(MODEL)_gen $(MODEL)_gres
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@if [[ "$(VERBOSE)" == "1" ]]; then $(XPAT) -l $(MODEL)_gres; fi
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## > Synthèse
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synth: simul_gpat ## Synthétise pour produire la netlist de porte, utilise gpat pour la convénience
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$(BOOM) $(MODEL)_v $(MODEL)_o
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$(BOOG) $(MODEL)_o $(MODEL)_o
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#@if [[ "$(VERBOSE)" == "1" ]]; then $(XSCH) -l $(MODEL)_o; fi
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place: synth ## Place les cellules du core
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$(PLACE) -margin 0.3 -mdl 10 -ring $(MODEL)_o $(MODEL)_p
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#@if [[ "$(VERBOSE)" == "1" ]]; then $(GRAAL) -l $(MODEL)_p; fi
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route: place ## Route le core
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$(ROUTE) -p $(MODEL)_p $(MODEL)_o $(MODEL)_o
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@if [[ "$(VERBOSE)" == "1" ]]; then $(GRAAL) -l $(MODEL)_o; fi
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ring: route ## Route le core et les plots
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cpp $(MODEL).h -DCORE=$(MODEL)_o | grep -v "^#" > $(MODEL)_chip.vst
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cpp $(MODEL).h -DPLOT | grep -v "^#" > $(MODEL)_chip.rin
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$(RING) $(MODEL)_chip $(MODEL)_chip
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@if [[ "$(VERBOSE)" == "1" ]]; then $(GRAAL) -l $(MODEL)_chip; fi
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s2r: druc ## Génère le format CIF
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$(S2R) -tv $(MODEL)_chip
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$(DREAL) -l $(MODEL)_chip
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@if [[ "$(VERBOSE)" == "1" ]]; then $(DREAL) -l $(MODEL)_chip; fi
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## > Vérification
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druc: ring ## Vérifie les règles de dessin de tous le circuit
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$(DRUC) $(MODEL)_o
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cougar_cell: s2r ## Extraction du coeur jusqu'aux cellules
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$(EXTC) -c $(MODEL)_o $(MODEL)_x
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cougar_tran: s2r ## Extraction du coeur jusqu'aux transistors
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$(EXTT) -t $(MODEL)_o $(MODEL)_x
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resimul_pat: cougar_cell ## Simule un jeu de patterns générés
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$(ASIM) -zd $(MODEL)_x patterns/$(MODEL)x $(MODEL)_resx
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@if [[ "$(VERBOSE)" == "1" ]]; then $(XPAT) -l $(MODEL)_resx; fi
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resimul_gpat: cougar_cell ## Simule un jeu de patterns générés
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export MODEL=$(MODEL) CYCLES=50 TYPE=NET; genpat patterns/$(MODEL)
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$(ASIM) -zd $(MODEL)_x $(MODEL)_genx $(MODEL)_gresx
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@if [[ "$(VERBOSE)" == "1" ]]; then $(XPAT) -l $(MODEL)_gresx; fi
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## Divers
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clean: ## Efface tous les fichiers intermédiaires
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rm -f $(MODEL)_*.* Makefile.*
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#define POWER_PORT ck,vdde,vddi,vsse,vssi : in bit
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#define POWER ck=>ck_p,vdde=>vdde,vddi=>vddi,vsse=>vsse,vssi=>vssi
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#ifdef PLOT
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east ( p_vddi p_vssi p_vdde p_vsse )
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west ( p_led1_0 p_led1_1 p_led1_2 p_led1_3 p_led1_4 p_led1_5 p_led1_6 p_raz p_led0_0 p_led0_1 )
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north ( p_led2_0 p_led2_1 p_led2_2 p_led2_3 p_led2_4 p_led2_5 p_led2_6 p_plus p_led0_2 p_led0_3 )
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south ( p_led3_0 p_led3_1 p_led3_2 p_led3_3 p_led3_4 p_led3_5 p_led3_6 p_ck p_led0_4 p_led0_5 p_led0_6 )
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#else
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ENTITY clicker_chip IS
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PORT (
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ck : IN bit;
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raz : IN bit;
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plus : IN bit;
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led0 : OUT bit_vector (0 to 6);
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led1 : OUT bit_vector (0 to 6);
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led2 : OUT bit_vector (0 to 6);
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led3 : OUT bit_vector (0 to 6);
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vddi, vssi : IN bit;
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vdde, vsse : IN bit
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);
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END clicker_chip;
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ARCHITECTURE chip OF clicker_chip IS
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component pi_sp port ( pad : in bit; t : out bit; POWER_PORT ); end component;
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component po_sp port ( i : in bit; pad : out bit; POWER_PORT ); end component;
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component pvdde_sp port ( POWER_PORT ); end component;
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component pvsse_sp port ( POWER_PORT ); end component;
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component pvddi_sp port ( POWER_PORT ); end component;
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component pvssi_sp port ( POWER_PORT ); end component;
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component CORE port(
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ck : IN bit;
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raz : IN bit;
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plus : IN bit;
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led0 : OUT bit_vector (0 to 6);
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led1 : OUT bit_vector (0 to 6);
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led2 : OUT bit_vector (0 to 6);
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led3 : OUT bit_vector (0 to 6);
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vdd, vss : IN bit
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);
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END component;
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signal ck_i, raz_i, ck_p, plus_i : bit;
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signal led0_i : bit_vector(0 to 6);
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signal led1_i : bit_vector(0 to 6);
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signal led2_i : bit_vector(0 to 6);
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signal led3_i : bit_vector(0 to 6);
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begin
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p_ck : pi_sp port map ( pad=>ck, t=>ck_i, POWER );
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p_raz : pi_sp port map ( pad=>raz, t=>raz_i, POWER );
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p_plus : pi_sp port map ( pad=>plus, t=>plus_i, POWER );
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p_led0_0 : pi_sp port map ( pad=>led0(0), t=>led0_i(0), POWER );
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p_led0_1 : pi_sp port map ( pad=>led0(1), t=>led0_i(1), POWER );
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p_led0_2 : pi_sp port map ( pad=>led0(2), t=>led0_i(2), POWER );
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p_led0_3 : pi_sp port map ( pad=>led0(3), t=>led0_i(3), POWER );
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p_led0_4 : pi_sp port map ( pad=>led0(4), t=>led0_i(4), POWER );
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p_led0_5 : pi_sp port map ( pad=>led0(5), t=>led0_i(5), POWER );
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p_led0_6 : pi_sp port map ( pad=>led0(6), t=>led0_i(6), POWER );
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p_led1_0 : pi_sp port map ( pad=>led1(0), t=>led1_i(0), POWER );
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p_led1_1 : pi_sp port map ( pad=>led1(1), t=>led1_i(1), POWER );
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p_led1_2 : pi_sp port map ( pad=>led1(2), t=>led1_i(2), POWER );
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p_led1_3 : pi_sp port map ( pad=>led1(3), t=>led1_i(3), POWER );
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p_led1_4 : pi_sp port map ( pad=>led1(4), t=>led1_i(4), POWER );
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p_led1_5 : pi_sp port map ( pad=>led1(5), t=>led1_i(5), POWER );
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p_led1_6 : pi_sp port map ( pad=>led1(6), t=>led1_i(6), POWER );
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p_led2_0 : pi_sp port map ( pad=>led2(0), t=>led2_i(0), POWER );
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p_led2_1 : pi_sp port map ( pad=>led2(1), t=>led2_i(1), POWER );
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p_led2_2 : pi_sp port map ( pad=>led2(2), t=>led2_i(2), POWER );
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p_led2_3 : pi_sp port map ( pad=>led2(3), t=>led2_i(3), POWER );
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p_led2_4 : pi_sp port map ( pad=>led2(4), t=>led2_i(4), POWER );
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p_led2_5 : pi_sp port map ( pad=>led2(5), t=>led2_i(5), POWER );
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p_led2_6 : pi_sp port map ( pad=>led2(6), t=>led2_i(6), POWER );
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p_led3_0 : pi_sp port map ( pad=>led3(0), t=>led3_i(0), POWER );
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p_led3_1 : pi_sp port map ( pad=>led3(1), t=>led3_i(1), POWER );
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p_led3_2 : pi_sp port map ( pad=>led3(2), t=>led3_i(2), POWER );
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p_led3_3 : pi_sp port map ( pad=>led3(3), t=>led3_i(3), POWER );
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p_led3_4 : pi_sp port map ( pad=>led3(4), t=>led3_i(4), POWER );
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p_led3_5 : pi_sp port map ( pad=>led3(5), t=>led3_i(5), POWER );
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p_led3_6 : pi_sp port map ( pad=>led3(6), t=>led3_i(6), POWER );
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p_vdde : pvdde_sp port map ( POWER );
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p_vsse : pvsse_sp port map ( POWER );
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p_vddi : pvddi_sp port map ( POWER );
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p_vssi : pvssi_sp port map ( POWER );
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clicker : CORE port map (
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ck => ck_i,
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raz => raz_i,
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plus => plus_i,
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led0 => led0_i(0 to 6),
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led1 => led1_i(0 to 6),
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led2 => led2_i(0 to 6),
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led3 => led3_i(0 to 6),
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vdd => vddi,
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vss => vssi
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);
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END chip;
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#endif
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ENTITY clicker IS
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PORT(
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ck : IN std_logic;
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plus : IN std_logic;
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raz : IN std_logic;
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led0 : OUT std_logic_vector (0 to 6);
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led1 : OUT std_logic_vector (0 to 6);
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led2 : OUT std_logic_vector (0 to 6);
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led3 : OUT std_logic_vector (0 to 6)
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);
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END clicker;
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ARCHITECTURE model OF clicker IS
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SIGNAL val0, val_new0 : std_logic_vector (3 downto 0);
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SIGNAL val1, val_new1 : std_logic_vector (3 downto 0);
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SIGNAL val2, val_new2 : std_logic_vector (3 downto 0);
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SIGNAL val3, val_new3 : std_logic_vector (3 downto 0);
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BEGIN
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val_new0 <= x"0" when raz OR (val0 = x"9")
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else val0 + 1 when plus
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else val0;
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val_new1 <= x"0" when raz OR (val1 = x"9")
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else val1 + 1 when (val0 = x"9")
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else val1;
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val_new2 <= x"0" when raz OR (val2 = x"9")
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else val2 + 1 when (val1 = x"9")
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else val2;
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|
||||
val_new3 <= x"0" when raz OR (val3 = x"9")
|
||||
else val3 + 1 when (val2 = x"9")
|
||||
else val3;
|
||||
|
||||
memoire :
|
||||
block (ck = '1' AND not ck'stable) begin
|
||||
val0 <= guarded val_new0;
|
||||
val1 <= guarded val_new1;
|
||||
val2 <= guarded val_new2;
|
||||
val3 <= guarded val_new3;
|
||||
end block;
|
||||
|
||||
with val0 select led0 (0 to 6) <=
|
||||
"1111110" when x"0",
|
||||
"0110000" when x"1",
|
||||
"1101101" when x"2",
|
||||
"1111001" when x"3",
|
||||
"0110011" when x"4",
|
||||
"1011011" when x"5",
|
||||
"0011111" when x"6",
|
||||
"1110000" when x"7",
|
||||
"1111111" when x"8",
|
||||
"1111011" when others;
|
||||
|
||||
with val1 select led1 (0 to 6) <=
|
||||
"1111110" when x"0",
|
||||
"0110000" when x"1",
|
||||
"1101101" when x"2",
|
||||
"1111001" when x"3",
|
||||
"0110011" when x"4",
|
||||
"1011011" when x"5",
|
||||
"0011111" when x"6",
|
||||
"1110000" when x"7",
|
||||
"1111111" when x"8",
|
||||
"1111011" when others;
|
||||
|
||||
with val2 select led2 (0 to 6) <=
|
||||
"1111110" when x"0",
|
||||
"0110000" when x"1",
|
||||
"1101101" when x"2",
|
||||
"1111001" when x"3",
|
||||
"0110011" when x"4",
|
||||
"1011011" when x"5",
|
||||
"0011111" when x"6",
|
||||
"1110000" when x"7",
|
||||
"1111111" when x"8",
|
||||
"1111011" when others;
|
||||
|
||||
with val3 select led3 (0 to 6) <=
|
||||
"1111110" when x"0",
|
||||
"0110000" when x"1",
|
||||
"1101101" when x"2",
|
||||
"1111001" when x"3",
|
||||
"0110011" when x"4",
|
||||
"1011011" when x"5",
|
||||
"0011111" when x"6",
|
||||
"1110000" when x"7",
|
||||
"1111111" when x"8",
|
||||
"1111011" when others;
|
||||
|
||||
END model;
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
#--------------------------------------------------------------------------------
|
||||
# Add an help rule to document a Makefile
|
||||
#
|
||||
# There is two kind of messages
|
||||
#
|
||||
# 1) for configuration variables
|
||||
# add #% at the beginning of a line followed by any text
|
||||
# then put the VARIABLE the next lines this way:
|
||||
# VARIABLE = value#% comment
|
||||
#
|
||||
# 2) for rules
|
||||
# add ## at the beginning of a line followed by any text
|
||||
# then write each rule this way:
|
||||
# rule: ## help message
|
||||
#
|
||||
# Makefile Example
|
||||
# ----------------
|
||||
# include help.mk
|
||||
#
|
||||
# #% MAIN CONFIGURATION
|
||||
# VAR1 = value1#% VAR1 is a example of variable
|
||||
#
|
||||
# #% OPTIONNAL CONFIGURATION
|
||||
# VAR2 = value2#% VAR2 is a example of variable
|
||||
#
|
||||
# ## GENERIC RULES
|
||||
# rule1: ## help message
|
||||
# rule1: dependant files
|
||||
#
|
||||
# rule2: ## help message
|
||||
# rule2: dependant files
|
||||
#
|
||||
# ## MISCELLANEOUS
|
||||
# rule3: ## help message
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
SHELL := /bin/bash # Use bash syntax
|
||||
R := $(shell tput -Txterm setaf 1) # RED
|
||||
G := $(shell tput -Txterm setaf 2) # GREEN
|
||||
Y := $(shell tput -Txterm setaf 3) # YELLOW
|
||||
C := $(shell tput -Txterm setaf 6) # CYAN
|
||||
W := $(shell tput -Txterm setaf 7) # WHITE
|
||||
Z := $(shell tput -Txterm sgr0) # RESET
|
||||
|
||||
help: ## Show this help.
|
||||
@echo ''
|
||||
@echo 'Usage:'
|
||||
@echo ' ${Y}make ${G}<target>${Z}'
|
||||
@echo ''
|
||||
@awk 'BEGIN {FS="[ ]*\\?=[ ]*|#%"}\
|
||||
/^#% .*$$/ \
|
||||
{printf "%s:\n", substr($$0,4); next}\
|
||||
/^[A-Za-z_-].*=.*#%.*$$/ \
|
||||
{printf " ${Y}%-15s?= ${R}%-12s${G}%s${Z}\n",$$1,$$2,$$3}' $(MAKEFILE_LIST)
|
||||
@echo ''
|
||||
@echo 'Targets:'
|
||||
@awk 'BEGIN {FS=":.*?## "} \
|
||||
/^[a-zA-Z_-]+:.*?##.*$$/ \
|
||||
{printf " ${Y}%-16s${G}%s${Z}\n", $$1, $$2;next}\
|
||||
/^## .*$$/ \
|
||||
{printf " ${C}%s${Z}\n", substr($$1,4)}' $(MAKEFILE_LIST)
|
||||
@echo ''
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
//--------------------------------------------------------------------------------------------------
|
||||
// Pattern Generator for the Clicker
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
#include "mygenpat.h"
|
||||
|
||||
int main ()
|
||||
{
|
||||
|
||||
/// Get Environment Variables As Arguments
|
||||
|
||||
char* MODEL = GETENV("MODEL","default");
|
||||
unsigned CYCLES = atoi(GETENV("CYCLES","100"));
|
||||
char* TYPE = GETENV("TYPE","BEH");
|
||||
|
||||
/// Define Filename
|
||||
|
||||
if (strcmp(TYPE,"BEH") == 0)
|
||||
DEF_GENPAT (toa("%s_gen",MODEL));
|
||||
else
|
||||
DEF_GENPAT (toa("%s_genx",MODEL));
|
||||
|
||||
/// External Signals (mandatory)
|
||||
|
||||
DECLAR ("ck", ":2", "B", IN, "", "");
|
||||
DECLAR ("raz", ":2", "B", IN, "", "");
|
||||
DECLAR ("plus", ":2", "B", IN, "", "");
|
||||
DECLAR ("vdd", ":2", "B", IN, "", "");
|
||||
DECLAR ("vss", ":2", "B", IN, "", "");
|
||||
DECLAR ("led0", ":2", "B", OUT, vector(0,6), "");
|
||||
DECLAR ("led1", ":2", "B", OUT, vector(0,6), "");
|
||||
DECLAR ("led2", ":2", "B", OUT, vector(0,6), "");
|
||||
DECLAR ("led3", ":2", "B", OUT, vector(0,6), "");
|
||||
|
||||
/// Internal Signals (optionnal)
|
||||
|
||||
if (strcmp(TYPE,"BEH") == 0) {
|
||||
DECLAR (toa("%s_v.%s",MODEL,"val0"), ":2", "X", REGISTER, vector(3,0), "");
|
||||
DECLAR (toa("%s_v.%s",MODEL,"val1"), ":2", "X", REGISTER, vector(3,0), "");
|
||||
DECLAR (toa("%s_v.%s",MODEL,"val2"), ":2", "X", REGISTER, vector(3,0), "");
|
||||
DECLAR (toa("%s_v.%s",MODEL,"val3"), ":2", "X", REGISTER, vector(3,0), "");
|
||||
} else {
|
||||
DECLAR (toa("%s","val0"), ":2", "X", SIGNAL, vector(3,0), "");
|
||||
DECLAR (toa("%s","val1"), ":2", "X", SIGNAL, vector(3,0), "");
|
||||
DECLAR (toa("%s","val2"), ":2", "X", SIGNAL, vector(3,0), "");
|
||||
DECLAR (toa("%s","val3"), ":2", "X", SIGNAL, vector(3,0), "");
|
||||
}
|
||||
/// Signal Values
|
||||
|
||||
AFFECT (cycle (0), "vdd", "1");
|
||||
AFFECT (cycle (0), "vss", "0");
|
||||
|
||||
AFFECT (cycle (0), "raz", "1"); // Only first cycle
|
||||
AFFECT (cycle (1), "raz", "0");
|
||||
|
||||
AFFECT (cycle (0), "plus", "1");
|
||||
|
||||
/// Clock Generator
|
||||
|
||||
int c;
|
||||
for (c = 0; c <= CYCLES; c++) {
|
||||
AFFECT (cycle (c), "ck", itoa (0));
|
||||
AFFECT (next_cycle (c), "ck", itoa (1));
|
||||
}
|
||||
|
||||
/// Save The Generated Patterns
|
||||
|
||||
SAV_GENPAT ();
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
in ck ;;
|
||||
in raz ;;
|
||||
in plus ;;
|
||||
in power(vss,vdd) X;;
|
||||
register clicker_v.val0 (3 downto 0) X;;
|
||||
register clicker_v.val1 (3 downto 0) X;;
|
||||
register clicker_v.val2 (3 downto 0) X;;
|
||||
register clicker_v.val3 (3 downto 0) X;;
|
||||
out led0 (0 to 6) B;;
|
||||
out led1 (0 to 6) B;;
|
||||
out led2 (0 to 6) B;;
|
||||
out led3 (0 to 6) B;;
|
||||
|
||||
BEGIN
|
||||
|
||||
: 0 1 1 1 * *******;
|
||||
: 1 1 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
|
||||
END;
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
in ck ;;
|
||||
in raz ;;
|
||||
in plus ;;
|
||||
in power(vss,vdd) X;;
|
||||
signal val (3 downto 0) X;;
|
||||
out led (0 to 6) B;;
|
||||
|
||||
BEGIN
|
||||
|
||||
: 0 1 1 1 * *******;
|
||||
: 1 1 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
: 1 0 1 1 * *******;
|
||||
: 0 0 1 1 * *******;
|
||||
|
||||
END;
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
//--------------------------------------------------------------------------------------------------
|
||||
// Generic Include File for genpat
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
#ifndef _MYGENPAT_H_
|
||||
#define _MYGENPAT_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include <math.h>
|
||||
#include <assert.h>
|
||||
#include "genpat.h"
|
||||
#include "alloca.h"
|
||||
#include "stdarg.h"
|
||||
#include "mut.h"
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// since it is not possible to get arguments with genpat,
|
||||
// we use environment variables. The GETENV() macro try to get
|
||||
// the variable env value and we can choose a default value for each
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
#define GETENV(var,def) getenv(var)?getenv(var):def
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Constantes générales
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
const PERIOD = 2;
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// rend la date du cycle n°i ou du cycle n°i + 1 demi-cycle
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
#define cycle(i) itoa(i*PERIOD)
|
||||
#define next_cycle(i) itoa(i*PERIOD + PERIOD/2)
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Fabriquer une chaine de caractères à partir d'un entier
|
||||
//
|
||||
// namealloc fait l'équivalent de strdup() mais en plus il teste que la chaine
|
||||
// en paramètre n'a pas déjà été allouée, si oui, namealloc rend
|
||||
// le pointeur sur la chaine déjà allouée, cette opération utilise
|
||||
// un dictionnaire (table de hachage)
|
||||
//
|
||||
// itoa(42) rend un pointeur sur "42"
|
||||
// itoa(42) rend LE MÊME pointeur sur "42"
|
||||
// itoa(0x42,4) rend "0x0042"
|
||||
// itoaX(0x42,1) rend "0x2"
|
||||
// itoaX(0x42,8) rend "0x00000042"
|
||||
// vector(A,B) rend "A downto B" or "A to B" selon la valeur de A et de B
|
||||
// toa("%s%d","test",3) rend "test3"
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
|
||||
static inline char *itoa (int entier)
|
||||
{
|
||||
char *str = (char *) alloca (32 * sizeof (char)); // allocation dans la pile
|
||||
|
||||
sprintf (str, "%d", entier);
|
||||
return namealloc (str); // utilise un dictionnaire
|
||||
}
|
||||
|
||||
static inline char *itoaX (int entier, int size)
|
||||
{
|
||||
int mask;
|
||||
|
||||
for (mask = 0; size; mask = (mask << 1) | 1, size--);
|
||||
char *str = (char *) alloca (32 * sizeof (char)); // allocation dans la pile
|
||||
|
||||
sprintf (str, "0x%0*x", size, entier & mask);
|
||||
return namealloc (str); // utilise un dictionnaire
|
||||
}
|
||||
|
||||
static inline char *vector (int from, int to)
|
||||
{
|
||||
char *str = (char *) alloca (32 * sizeof (char)); // allocation dans la pile
|
||||
if (from > to)
|
||||
sprintf (str, "%d downto %d", from, to);
|
||||
else
|
||||
sprintf (str, "%d to %d", from, to);
|
||||
return namealloc (str); // utilise un dictionnaire
|
||||
}
|
||||
|
||||
static inline char *toa (char *fmt, ...)
|
||||
{
|
||||
char str[256];
|
||||
va_list ap;
|
||||
va_start (ap, fmt);
|
||||
vsnprintf (str, sizeof(str), fmt, ap);
|
||||
va_end (ap);
|
||||
return namealloc (str); // utilise un dictionnaire
|
||||
}
|
||||
|
||||
#endif //_MYGENPAT_H_
|
||||
|
|
@ -0,0 +1,559 @@
|
|||
# 20230301
|
||||
# ---------------------------------------------------------------------------
|
||||
# For SkyWater130
|
||||
# ---------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
# -------------------------------------------------------------------
|
||||
# globals define
|
||||
# -------------------------------------------------------------------
|
||||
|
||||
define physical_grid 0.005
|
||||
define lambda 0.140
|
||||
|
||||
table cif_layer
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name cif_name
|
||||
# -------------------------------------------------------------------
|
||||
rds_nwell nwel
|
||||
# rds_pwell pwel
|
||||
rds_activ active
|
||||
rds_ntie nplus
|
||||
rds_ptie pplus
|
||||
rds_nimp nplus
|
||||
rds_pimp pplus
|
||||
rds_poly poly
|
||||
rds_alu1 metal1
|
||||
rds_alu2 metal2
|
||||
rds_alu3 metal3
|
||||
rds_alu4 metal4
|
||||
rds_alu5 metal5
|
||||
rds_alu6 metal6
|
||||
rds_cont contact
|
||||
rds_via1 via1
|
||||
rds_via2 via2
|
||||
rds_via3 via3
|
||||
rds_via4 via4
|
||||
rds_via5 via5
|
||||
rds_cpas pad
|
||||
end
|
||||
|
||||
table gds_layer
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name gds_number
|
||||
# -------------------------------------------------------------------
|
||||
rds_nwell 3
|
||||
# rds_pwell 8
|
||||
rds_activ 6
|
||||
rds_ptie 25
|
||||
rds_ntie 26
|
||||
rds_pimp 25
|
||||
rds_nimp 26
|
||||
rds_poly 17 149
|
||||
rds_alu1 31 131
|
||||
rds_alu2 32 132
|
||||
rds_alu3 33 133
|
||||
rds_alu4 34 134
|
||||
rds_alu5 35 135
|
||||
rds_alu6 36 136
|
||||
rds_cont 30
|
||||
rds_via1 51
|
||||
rds_via2 52
|
||||
rds_via3 53
|
||||
rds_via4 54
|
||||
rds_via5 55
|
||||
rds_cpas 43
|
||||
end
|
||||
|
||||
table lynx_resistor
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name square_resistor(ohm/square) # typical values
|
||||
# -------------------------------------------------------------------
|
||||
rds_poly 48
|
||||
rds_alu1 13
|
||||
rds_alu2 0.125
|
||||
rds_alu3 0.125
|
||||
rds_alu4 0.047
|
||||
rds_alu5 0.047
|
||||
rds_alu6 0.029
|
||||
rds_cont 15
|
||||
rds_via1 152
|
||||
rds_via2 4.5
|
||||
rds_via3 3.4
|
||||
rds_via4 3.4
|
||||
rds_via5 0.38
|
||||
end
|
||||
|
||||
table lynx_capa
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name area_capa(pif/um^2) peri_capa(pif/um)
|
||||
# -------------------------------------------------------------------
|
||||
rds_poly 25.2e-6 51.8e-6 # Ca max POLY_NWELL 2Cf0 max POLY_NWELL
|
||||
rds_alu1 2.6e-5 8.5e-5 # Ca max M1_NWELL 2Cf0 max M1_NWELL
|
||||
rds_alu2 1.6e-5 7.9e-5 # Ca max M2_NWELL 2Cf0 max M2_NWELL
|
||||
rds_alu3 8.0e-6 6.8e-5 # Ca max M3_NWELL 2Cf0 max M3_NWELL
|
||||
rds_alu4 6.0e-6 6.0e-5 # Ca max M4_NWELL 2Cf0 max M4_NWELL
|
||||
rds_alu5 6.0e-6 6.0e-5 # hyp
|
||||
rds_alu6 6.0e-6 6.0e-5
|
||||
end
|
||||
|
||||
table lynx_capa_poly
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name area_capa(pif/um^2) peri_capa(pif/um)
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table lynx_capa_poly2
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name area_capa(pif/um^2) peri_capa(pif/um)
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table lynx_capa_alu1
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name area_capa(pif/um^2) peri_capa(pif/um)
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table lynx_capa_alu2
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name area_capa(pif/um^2) peri_capa(pif/um)
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table lynx_capa_alu3
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name area_capa(pif/um^2) peri_capa(pif/um)
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table lynx_capa_alu4
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name area_capa(pif/um^2) peri_capa(pif/um)
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table lynx_capa_alu5
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name area_capa(pif/um^2) peri_capa(pif/um)
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
table mbk_to_rds_segment
|
||||
# ----------------------------------------------------------------------------------
|
||||
# mbk_name rds_name1 dlr dwr offset mode rds_name2 dlr dwr offset mode
|
||||
# ----------------------------------------------------------------------------------
|
||||
|
||||
nwell rds_nwell vw 0.460 0.280 .0 all\
|
||||
rds_pimp vw 0.225 0.170 .0 all
|
||||
|
||||
pwell rds_pwell vw 0.460 0.280 .0 all\
|
||||
rds_nimp vw 0.225 0.170 .0 all
|
||||
|
||||
ndif rds_activ vw 0.070 0.000 .0 all\
|
||||
rds_ndif vw 0.070 0.000 .0 ext
|
||||
|
||||
pdif rds_activ vw 0.070 0.000 .0 all\
|
||||
rds_pdif vw 0.070 0.000 .0 ext
|
||||
|
||||
ntie rds_activ vw 0.145 -0.130 .0 all\
|
||||
rds_ntie vw 0.270 0.120 .0 all\
|
||||
rds_nwell vw 0.460 0.510 .0 all
|
||||
|
||||
ptie rds_activ vw 0.145 -0.130 .0 all\
|
||||
rds_ptie vw 0.270 0.120 .0 all\
|
||||
rds_pwell vw 0.460 0.510 .0 all
|
||||
|
||||
ntrans rds_poly vw -0.075 0.010 .0 all\
|
||||
rds_activ vw -0.210 0.560 .0 drc\
|
||||
rds_ndif lcw -0.210 0.280 0.005 ext\
|
||||
rds_ndif rcw -0.210 0.280 0.005 ext
|
||||
|
||||
ptrans rds_poly vw -0.075 0.010 .0 all\
|
||||
rds_activ vw -0.210 0.560 .0 drc\
|
||||
rds_pdif lcw -0.210 0.280 0.005 ext\
|
||||
rds_pdif rcw -0.210 0.280 0.005 ext
|
||||
|
||||
poly rds_poly vw 0.075 0.010 .0 all
|
||||
|
||||
alu1 rds_alu1 vw 0.165 0.050 .0 all
|
||||
calu1 rds_alu1 vw 0.165 0.050 .0 all
|
||||
talu1 rds_talu1 vw 0.165 0.050 .0 all
|
||||
|
||||
alu2 rds_alu2 vw 0.165 0.050 .0 all
|
||||
calu2 rds_alu2 vw 0.165 0.050 .0 all
|
||||
talu2 rds_talu2 vw 0.165 0.050 .0 all
|
||||
|
||||
alu3 rds_alu3 vw 0.165 0.050 .0 all
|
||||
calu3 rds_alu3 vw 0.165 0.050 .0 all
|
||||
talu3 rds_talu3 vw 0.165 0.050 .0 all
|
||||
end
|
||||
|
||||
table mbk_to_rds_connector
|
||||
# -------------------------------------------------------------------
|
||||
# mbk_name rds_name der dwr
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table mbk_to_rds_reference
|
||||
# -------------------------------------------------------------------
|
||||
# mbk_name rds_name width
|
||||
# -------------------------------------------------------------------
|
||||
ref_ref rds_ref 0.330
|
||||
ref_con rds_ref 0.330
|
||||
end
|
||||
|
||||
table mbk_to_rds_via
|
||||
# -------------------------------------------------------------------
|
||||
# mbk_name rds_name1 width mode rds_name2 width mode ...
|
||||
## ------------------------------------------------------------------
|
||||
cont_body_n \
|
||||
rds_cont 0.170 all\
|
||||
rds_alu1 0.330 all\
|
||||
rds_activ 0.290 drc\
|
||||
rds_ntie 0.290 ext
|
||||
|
||||
cont_body_p \
|
||||
rds_cont 0.170 all\
|
||||
rds_alu1 0.330 all\
|
||||
rds_activ 0.290 drc\
|
||||
rds_ptie 0.290 ext
|
||||
|
||||
cont_dif_n \
|
||||
rds_cont 0.170 all\
|
||||
rds_alu1 0.330 all\
|
||||
rds_activ 0.420 drc\
|
||||
rds_ndif 0.420 ext
|
||||
|
||||
cont_dif_p \
|
||||
rds_cont 0.170 all\
|
||||
rds_alu1 0.330 all\
|
||||
rds_activ 0.420 drc\
|
||||
rds_pdif 0.420 ext
|
||||
|
||||
cont_poly \
|
||||
rds_cont 0.170 all\
|
||||
rds_poly 0.290 all\
|
||||
rds_alu1 0.330 all
|
||||
|
||||
cont_via \
|
||||
rds_via1 0.170 all\
|
||||
rds_alu1 0.330 all\
|
||||
rds_alu2 0.330 all
|
||||
|
||||
cont_via2 \
|
||||
rds_via2 0.170 all\
|
||||
rds_alu2 0.330 all\
|
||||
rds_alu3 0.330 all
|
||||
end
|
||||
|
||||
table mbk_to_rds_bigvia_hole
|
||||
# -------------------------------------------------------------------
|
||||
# mbk_via_name rds_hole_name side step mode
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table mbk_to_rds_bigvia_metal
|
||||
# -------------------------------------------------------------------
|
||||
# mbk_via_name rds_name dwr overlap mode
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table mbk_to_rds_turnvia
|
||||
# -------------------------------------------------------------------
|
||||
# mbk_name rds_name dwr mode
|
||||
# -------------------------------------------------------------------
|
||||
cont_turn1 rds_alu1 0.050 all
|
||||
cont_turn2 rds_alu1 0.050 all
|
||||
cont_turn3 rds_alu1 0.050 all
|
||||
end
|
||||
|
||||
table lynx_bulk_implicit
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name type[explicit|implicit]
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table lynx_transistor
|
||||
# -------------------------------------------------------------------
|
||||
# mbk_name trans_name compostion
|
||||
# -------------------------------------------------------------------
|
||||
end
|
||||
|
||||
table lynx_diffusion
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name compostion
|
||||
# -------------------------------------------------------------------
|
||||
rds_ndif rds_activ 1 rds_nimp 1 rds_nwell 0
|
||||
rds_pdif rds_activ 1 rds_pimp 1 rds_nwell 1
|
||||
rds_ntie rds_activ 1 rds_nimp 1 rds_nwell 1
|
||||
rds_ptie rds_activ 1 rds_pimp 1 rds_nwell 0
|
||||
end
|
||||
|
||||
table lynx_graph
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name in_contact_with rds_name1 rds_name2 ...
|
||||
# -------------------------------------------------------------------
|
||||
rds_ndif rds_cont rds_ndif
|
||||
rds_pdif rds_cont rds_pdif
|
||||
rds_poly rds_cont rds_poly
|
||||
rds_cont rds_pdif rds_ndif rds_poly rds_alu1 rds_cont
|
||||
rds_alu1 rds_cont rds_via1 rds_ref rds_alu1
|
||||
rds_ref rds_cont rds_via1 rds_alu1 rds_ref
|
||||
rds_alu2 rds_via1 rds_via2 rds_alu2
|
||||
rds_alu3 rds_via2 rds_alu3
|
||||
end
|
||||
|
||||
table s2r_oversize_denotch
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name oversized_value_for_denotching
|
||||
# -------------------------------------------------------------------
|
||||
rds_nwell 0.635
|
||||
rds_pwell 0.635
|
||||
rds_poly 0.100
|
||||
rds_alu1 0.080
|
||||
rds_alu2 0.080
|
||||
rds_alu3 0.080
|
||||
rds_activ 0.130
|
||||
rds_ntie 0.190
|
||||
rds_ptie 0.190
|
||||
rds_nimp 0.190
|
||||
rds_pimp 0.190
|
||||
end
|
||||
|
||||
table s2r_bloc_ring_width
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name ring_width_to_copy_up
|
||||
# -------------------------------------------------------------------
|
||||
rds_nwell 0. # [ RD_NWEL ]
|
||||
rds_pwell 0. # [ RD_PWEL ]
|
||||
rds_poly 0. # [ RD_POLY ]
|
||||
rds_alu1 0. # [ RD_ALU1 ]
|
||||
rds_alu2 0. # [ RD_ALU2 ]
|
||||
rds_alu3 0. # [ RD_ALU3 ]
|
||||
rds_activ 0. # [ RD_ACTI ]
|
||||
rds_ntie 0. # [ RD_NIMP ]
|
||||
rds_ptie 0. # [ RD_PIMP ]
|
||||
rds_nimp 0. # [ RD_NIMP ]
|
||||
rds_pimp 0. # [ RD_PIMP ]
|
||||
end
|
||||
|
||||
table s2r_minimum_layer_width
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name min_layer_width_to_keep
|
||||
# -------------------------------------------------------------------
|
||||
rds_nwell 0.840
|
||||
rds_pwell 0.840
|
||||
rds_poly 0.150
|
||||
rds_alu1 0.330
|
||||
rds_alu2 0.330
|
||||
rds_alu3 0.330
|
||||
rds_activ 0.420
|
||||
rds_ntie 0.380
|
||||
rds_ptie 0.380
|
||||
rds_nimp 0.380
|
||||
rds_pimp 0.380
|
||||
end
|
||||
|
||||
table s2r_post_treat
|
||||
# -------------------------------------------------------------------
|
||||
# rds_name s2r_must_treat_or_not second_layer_whenever_scotch
|
||||
# -------------------------------------------------------------------
|
||||
rds_nwell treat null
|
||||
rds_pwell treat null
|
||||
rds_poly treat null
|
||||
rds_activ treat null
|
||||
rds_ntie treat rds_pimp
|
||||
rds_ptie treat rds_nimp
|
||||
rds_nimp treat rds_ptie
|
||||
rds_pimp treat rds_ntie
|
||||
rds_alu1 treat null
|
||||
rds_alu2 treat null
|
||||
rds_alu3 treat null
|
||||
rds_cont notreat null
|
||||
end
|
||||
|
||||
DRC_RULES
|
||||
|
||||
layer RDS_NWELL 0.840 ;
|
||||
layer RDS_NTIE 0.380 ;
|
||||
layer RDS_PTIE 0.380 ;
|
||||
layer RDS_NIMP 0.380 ;
|
||||
layer RDS_PIMP 0.380 ;
|
||||
layer RDS_ACTIV 0.420 ;
|
||||
layer RDS_CONT 0.170 ;
|
||||
layer RDS_POLY 0.150 ;
|
||||
layer RDS_ALU1 0.170 ;
|
||||
layer RDS_ALU2 0.170 ;
|
||||
layer RDS_ALU3 0.170 ;
|
||||
layer RDS_USER0 0.005 ;
|
||||
layer RDS_USER1 0.005 ;
|
||||
layer RDS_USER2 0.005 ;
|
||||
|
||||
regles
|
||||
|
||||
# note : ``min'' is different from ``>=''.
|
||||
# min is applied on polygons and >= is applied on rectangles.
|
||||
# there is the same difference between max and <=.
|
||||
# >= is faster than min, but min must be used where it is
|
||||
# required to consider polygons, for example distance of
|
||||
# two objects in the same layer
|
||||
#
|
||||
# ----------------------------------------------------------
|
||||
|
||||
# check the nwell shapes
|
||||
# ----------------------
|
||||
caracterise RDS_NWELL (
|
||||
regle 1 : largeur >= 0.840 ;
|
||||
regle 2 : longueur_inter min 0.840 ;
|
||||
regle 3 : notch >= 1.270 ;
|
||||
);
|
||||
relation RDS_NWELL , RDS_NWELL (
|
||||
regle 4 : distance axiale min 1.270 ;
|
||||
);
|
||||
relation RDS_NWELL , RDS_ACTI (
|
||||
regle 5 : distance axiale min 0.340 ;
|
||||
);
|
||||
|
||||
# check the RDS_PIMP shapes
|
||||
# -------------------------
|
||||
caracterise RDS_PIMP (
|
||||
regle 6 : surface min 0.255 ;
|
||||
regle 7 : largeur >= 0.380 ;
|
||||
regle 8 : longueur_inter min 0.380 ;
|
||||
regle 9 : notch >= 0.380 ;
|
||||
);
|
||||
relation RDS_PIMP , RDS_PIMP (
|
||||
regle 10 : distance axiale min 0.380 ;
|
||||
);
|
||||
|
||||
# check the RDS_NIMP shapes
|
||||
# -------------------------
|
||||
caracterise RDS_NIMP (
|
||||
regle 11 : surface min 0.265 ;
|
||||
regle 12 : largeur >= 0.380 ;
|
||||
regle 13 : longueur_inter min 0.380 ;
|
||||
regle 14 : notch >= 0.380 ;
|
||||
);
|
||||
relation RDS_NIMP , RDS_NIMP (
|
||||
regle 15 : distance axiale min 0.380 ;
|
||||
);
|
||||
|
||||
# check the RDS_PTIE shapes
|
||||
# -------------------------
|
||||
caracterise RDS_PTIE (
|
||||
regle 16 : surface min 0.255 ;
|
||||
regle 17 : largeur >= 0.380 ;
|
||||
regle 18 : longueur_inter min 0.380 ;
|
||||
regle 19 : notch >= 0.380 ;
|
||||
);
|
||||
relation RDS_PTIE , RDS_PTIE (
|
||||
regle 20 : distance axiale min 0.380 ;
|
||||
);
|
||||
|
||||
# check the RDS_NTIE shapes
|
||||
# -------------------------
|
||||
caracterise RDS_NTIE (
|
||||
regle 21 : surface min 0.265 ;
|
||||
regle 22 : largeur >= 0.380 ;
|
||||
regle 23 : longueur_inter min 0.380 ;
|
||||
regle 24 : notch >= 0.380 ;
|
||||
);
|
||||
relation RDS_NTIE , RDS_NTIE (
|
||||
regle 25 : distance axiale min 0.380 ;
|
||||
);
|
||||
|
||||
# check the RDS_ACTI shapes
|
||||
# -------------------------
|
||||
caracterise RDS_ACTI (
|
||||
regle 26 : surface min 0.000 ;
|
||||
regle 27 : largeur >= 0.420 ;
|
||||
regle 28 : longueur_inter min 0.420 ;
|
||||
regle 29 : notch >= 0.270 ;
|
||||
);
|
||||
relation RDS_ACTI, RDS_ACTI (
|
||||
regle 30 : distance axiale min 0.270 ;
|
||||
);
|
||||
|
||||
# check the RDS_NIMP RDS_PTIE exclusion
|
||||
# -------------------------------------
|
||||
define RDS_NIMP , RDS_PTIE intersection -> NPIMP;
|
||||
caracterise NPIMP (
|
||||
regle 31 : largeur = 0. ;
|
||||
);
|
||||
undefine NPIMP;
|
||||
|
||||
# check the RDS_NTIE RDS_PIMP exclusion
|
||||
# -------------------------------------
|
||||
define RDS_NTIE , RDS_PIMP intersection -> NPIMP;
|
||||
caracterise NPIMP (
|
||||
regle 32 : largeur = 0. ;
|
||||
);
|
||||
undefine NPIMP;
|
||||
|
||||
# check the RDS_POLY shapes
|
||||
# -------------------------
|
||||
caracterise RDS_POLY (
|
||||
regle 33 : largeur >= 0.150 ;
|
||||
regle 34 : longueur_inter min 0.150 ;
|
||||
regle 35 : notch >= 0.210 ;
|
||||
);
|
||||
relation RDS_POLY , RDS_POLY (
|
||||
regle 36 : distance axiale min 0.210 ;
|
||||
);
|
||||
|
||||
define RDS_ACTI , RDS_POLY intersection -> channel;
|
||||
|
||||
# check the channel shapes
|
||||
# -------------------------
|
||||
caracterise channel (
|
||||
regle 37 : notch >= 0.210 ;
|
||||
);
|
||||
relation channel , channel (
|
||||
regle 38 : distance axiale min 0.210 ;
|
||||
);
|
||||
|
||||
undefine channel;
|
||||
|
||||
define RDS_ACTI , RDS_CONT intersection -> cont_diff;
|
||||
|
||||
relation RDS_POLY , cont_diff (
|
||||
regle 39 : distance axiale >= 0.250 ;
|
||||
);
|
||||
|
||||
undefine cont_diff;
|
||||
|
||||
# check RDS_ALU1 shapes
|
||||
# ---------------------
|
||||
caracterise RDS_ALU1 (
|
||||
regle 40 : surface min 0.060 ;
|
||||
regle 41 : largeur >= 0.170 ;
|
||||
regle 42 : longueur_inter min 0.170 ;
|
||||
regle 43 : notch >= 0.170 ;
|
||||
);
|
||||
relation RDS_ALU1 , RDS_ALU1 (
|
||||
regle 44 : distance axiale min 0.170 ;
|
||||
);
|
||||
|
||||
# check any_via layers, stacking are free
|
||||
# ---------------------------------------
|
||||
relation RDS_CONT , RDS_CONT (
|
||||
regle 45 : distance axiale >= 0.170 ;
|
||||
);
|
||||
|
||||
caracterise RDS_CONT (
|
||||
regle 46 : largeur = 0.170 ;
|
||||
regle 47 : longueur = 0.170 ;
|
||||
);
|
||||
|
||||
# check RDS_POLY is distant from activ zone of transistor
|
||||
# -------------------------------------------------------
|
||||
relation RDS_POLY , RDS_ACTIV (
|
||||
regle 48 : distance axiale >= 0.075 ;
|
||||
);
|
||||
|
||||
fin regles
|
||||
DRC_COMMENT
|
||||
END_DRC_COMMENT
|
||||
END_DRC_RULES
|
||||
|
|
@ -34,6 +34,63 @@ $$index = (vaddr & (0x1FF000 << (9 × (lvl-1)))) >> (12 + (9 × (lvl-1)))$$
|
|||
|
||||
### Q2
|
||||
|
||||
|
||||
fait.
|
||||
|
||||
## Exercice 3
|
||||
|
||||
### Q1
|
||||
|
||||
L'adresse 0x2000000030 correspond à la zone de pile (stack) utilisateur,
|
||||
on peut donc supposer que la faute de page est provoquée par un appel de fonction
|
||||
effectué depuis le code utilisateur.
|
||||
|
||||
### Q2
|
||||
|
||||
+----------------------+ 0xffffffffffffffff
|
||||
| Higher half |
|
||||
| (unused) |
|
||||
+----------------------+ 0xffff800000000000
|
||||
| (impossible address) |
|
||||
+----------------------+ 0x00007fffffffffff
|
||||
| User |
|
||||
| (text + data + heap) |
|
||||
+----------------------+ 0x2000000000
|
||||
| User |
|
||||
| (stack) |
|
||||
+----------------------+ 0x40000000
|
||||
| Kernel |
|
||||
| (valloc) |
|
||||
+----------------------+ 0x201000
|
||||
| Kernel |
|
||||
| (APIC) |
|
||||
+----------------------+ 0x200000
|
||||
| Kernel |
|
||||
| (text + data) |
|
||||
+----------------------+ 0x100000
|
||||
| Kernel |
|
||||
| (BIOS + VGA) |
|
||||
+----------------------+ 0x0
|
||||
|
||||
Pour toutes les tâches, les zones communes sont évidemment celles du noyau (car
|
||||
il faut pouvoir effectuer des appels système notamment, avoir un buffer VGA
|
||||
fonctionnel).
|
||||
|
||||
On va donc avoir en commun :
|
||||
|
||||
+----------------------+ 0x40000000
|
||||
| Kernel |
|
||||
| (valloc) |
|
||||
+----------------------+ 0x201000
|
||||
| Kernel |
|
||||
| (APIC) |
|
||||
+----------------------+ 0x200000
|
||||
| Kernel |
|
||||
| (text + data) |
|
||||
+----------------------+ 0x100000
|
||||
| Kernel |
|
||||
| (BIOS + VGA) |
|
||||
+----------------------+ 0x0
|
||||
|
||||
### Q3
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ void main_multiboot2(void *mb2)
|
|||
|
||||
fake.pgt = store_cr3();
|
||||
new = alloc_page();
|
||||
map_page(&fake, 0xFFFFFFFFFFF, new);
|
||||
map_page(&fake, 0x201000, new);
|
||||
|
||||
printk("-----------\n\n");
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue